CMOS logarithmic curvature-corrected voltage reference using a multiple differential structure

Two original superior-order curvature-corrected voltage references was presented. In order to improve the temperature behavior of the circuits, double differential structures was used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary to absolute temperature) voltage generator was proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference. The superior-order curvature-correction was implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (proportional to absolute temperature) and PTAT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The SPICE simulations confirm the theoretical estimated results, showing temperature coefficients under 11 ppm/K for an extended input range 173K < T < 423K and for a supply voltage of 2.5V and a current consumption of about 1muA

In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3 V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behaviour of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13 µm IBM CMOS technology parameters have been used for simulation.

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ?, respectively), ? parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.

: A Dynamic Threshold MOS (DTMOS) transistor has the unique ability to operate at 0.5V with high speed and current wile delivering a low off state leakage. This project investigated the possibility of using DTMOS at Vdd > 0.5V to achieve higher circuit performance.

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction in comparison with CMOS Schmitt triggers, at the cost of a slight increase in delay. The performance characteristics of Schmitt trigger gates have been analyzed in term of power dissipation and delay using predictive Technology models at 180nm technology node for both CMOS and VTCMOS Schmitt trigger.

Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation

High linear voltage reference circuitry is designed and implemented in TSMC 0.13 mum and 0.18 mum CMOS technology. Previous research has proposed the use of MOS transistors operating in the weak inversion region to replace the bipolar devices in conventional PTAT (proportional to absolute temperature) circuits. However, such solutions often have linearity problem in high temperature region due to the current leaking devices in modern deep sub micron and nano-scale CMOS technology. The proposed circuit utilized temperature complementation technique on two voltage references, PTAT and IOAT (independent of absolute temperature) references, to enhance the linearity and produce a more stable lOAT voltage reference. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55degC to 170degC. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts.

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system's power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- μm CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF's excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of -40 °C-120 °C and supply voltage range of 1.2-1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. The circuit is designed in the 0.18μm CMOS technology. The simulation results show that the amplifier has a 91dB open-loop DC gain and a unity gain-bandwidth of 111.4 kHz while operating at 0.4V supply voltage. This technique show remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair technique. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical applications.

This paper presents an ultra-low power operational amplifier (opamp) with high gain and high common-mode rejection ratio (CMRR) in 45nm CMOS technology. It uses a bulk-driven differential pair in the input stage to facilitate low voltage design and to achieve a high input common-mode range (ICMR). In addition, the design employs an auxiliary differential pair that utilizes dynamic threshold MOS (DTMOS) technique to enhance the effective transconductance and hence achieves high gain and high unity-gain bandwidth (UGB). All the transistors are biased to operate in subthreshold region in order to minimize power consumption. Simulation with Cadence Virtuoso for 350 mV of supply and a load capacitance of 1 pF, yields a DC gain of 77.03 dB, CMRR of 130.8 dB, UGB of 456.9 kHz and a phase margin of 82.47° for a power consumption of 21.75 nW.

This brief presents a CMOS voltage reference for ultra-low-power applications, such as in implementable medical devices and energy harvesting-based wireless sensor nodes. In these applications, excellent capabilities to reject interference from power sources and work in low voltage to extend survival periods are critical for the voltage references. A transistor size-ratio determined current generator with high process and voltage independence is implemented by two same-threshold-voltage NMOS transistors, hence obtaining the precise reference voltage with an active load. The proposed circuit is fabricated in a standard 0.18μm CMOS process. Measurement results show that the prototype design provides a 210-mV reference with only 0.027% line sensitivity with a supply voltage from 1.8 V down to 0.4 V. The power supply ripple rejection at 10 Hz, 1 KHz, and 1 MHz is -59, 47, and 53 dB, respectively. The temperature coefficient is 82 ppm/°C in the temperature range from -40°C to +140 °C. Furthermore, the power consumption is only 9.6 nW at room temperature and the active area is 0.021 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper proposes an all MOSFET transistor-based voltage reference with ultra-low power consumption and high PSRR for Internet of Things applications. The reference voltage is computed using the gate source voltages of the five NMOS transistors, excluding the use of any transistors with high threshold voltages. To provide a steady clamping voltage for the current source, a supply voltage stability circuit with a current source is added which enhances the proposed voltage reference line sensitivity and PSRR. It has been designed and simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology to simulate the proposed voltage reference where all MOSFETs function in the subthreshold region with a 0.5[Formula: see text]V minimum supply voltage. The proposed voltage reference produces a reference voltage of 129.7[Formula: see text]mV with a supply voltage range of 0.5–3[Formula: see text]V. Based on simulation results, the proposed voltage reference has an active area of 0.001[Formula: see text]mm2, requires 11.2[Formula: see text]pW of power and has a line sensitivity of 0.021%/V. For a temperature range of [Formula: see text]40∘C to [Formula: see text]C, the circuit achieves a temperature coefficient of 38.2[Formula: see text]ppm/∘C. The power supply rejection ratio of the proposed voltage reference is [Formula: see text]101.5[Formula: see text]dB at 10[Formula: see text]Hz and [Formula: see text]90[Formula: see text]dB at 100[Formula: see text]Hz. The output noise at 100[Formula: see text]Hz and 1[Formula: see text]kHz is 4.68[Formula: see text]and 4.22[Formula: see text][Formula: see text]V/[Formula: see text]Hz, respectively.

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.