Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pair-based ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.

This paper deals with the design and analysis of the frequency of ring oscillators using the CMOS 45nm, 32nm, 22nm in a Symica simulation tool. A Ring Oscillator is an effective device made up of an odd number of NOT gates and its output runs between two levels of power standing up and down. There are many challenges ahead while designing a CMOS ring oscillator that can be delay, sound, and glitches. CMOS is the technology of choice for several applications, low-power CMOS oscillators are in high demand. The frequency of a CMOS ring oscillator was measured using waveform time zones for five, seven, and nine phases. This aids in the comparison of ring oscillators at various technology nodes and it is observed that the frequency is found to be maximum at a five-stage ring oscillator in each case i.e. 12.97GHz at 45 nm, 8.25GHz at 32 nm, 4.74GHz at 22 nm.

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

This paper presents a design for a voltage and current reference (VCR) that utilizes a 0.18-lm CMOS process. The design employs stacked-diode MOS-transistors (SDMT) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of -40°C to 130°C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately 25,000 μm2.

This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the adding of a CR differentiators-based MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase noise. Using 0.35 µm CMOS technology, simulation results show that applying the technique to the simple ring oscillator allows a frequency oscillation improvement of 78 %. Also, simulations show that frequency improvement can reach 250 % if the technique is associated to a positive feedback.

In this paper, a 24GHz frequency source for low phase noise is presented in a 0.18µm CMOS process. The 24GHz frequency source chip is composed of a 12GHz voltage controlled oscillator (VCO) and a 24GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17dBc/Hz at a 1MHz offset frequency and -20.95dB at 23.19GHz frequency, respectively. The measured frequency tuning range is from 23.19GHz to 24.76GHz drawing 2.72mA at a supply voltage of 1.8V not including an output buffer.

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

A wide locking range injection-locked prescaler based on CMOS ring oscillators in the 0.25-¿m CMOS process is described. The prescaler¿s free-running frequency is 1.47 GHz, and the locking range covers from 1 GHz to 2.4 GHz with in-phase and quadrature output. The prescaler dissipates 1.9 mA from a 3.3-V power supply.

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

This study presents an ultra-low-power, low-phase noise, and small-size voltage-controlled ring oscillator for use in implantable electronics operating in the Medical Implant Communication Service (MICS) frequency band and 65-nm IBM CMOS technology. This five-stage voltage-controlled ring oscillator does not require external inductor and capacitor similar to other LC oscillators, and hence, requires very small die area. A new methodology to design them has been employed in this study, and for optimizing the design of this voltage-controlled oscillator (VCO), the phase noise and power consumption of five-stage ring oscillators have been formulated and simulated for different sizes of transistors. The simulated phase noise of this VCO was -111 dBc/Hz at 1 MHz offset from a 400-MHz center frequency. The power consumption of VCO was 158 μW. This VCO has a tuning range from 352 to 454 MHz for tuning within the MICS band frequency, and frequency correction accounts for process supply voltage and temperature effects.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This manuscript presents the design of a low phase noise, high figure of merit (FoM) single-ended octagonal ring oscillator (RO). The proposed RO employs the pulse injection (PI) technique for performance enhancement. The PI technique is used for suppression of phase noise and spurious harmonics. Besides, a novel voltage dependent phase shifter is employed. The proposed RO has an output signal with voltage controlled phase. Different output signal phases can be obtained employing different selected voltages to control the output signal phase. The proposed injection locked ring oscillator (ILRO) represents a suitable implementation for phase shift keying. The proposed ILRO has a measured oscillation frequency of 4.9 GHz with a fine tuning range of 500 MHz. It has a measured phase noise of −126.17 dBc/Hz @ 1MHz offset while consuming only 4.8 mW of DC power. The proposed ILRO has a FoM of −193.17 dBc/Hz. This RO has been designed and implemented in 0.18 µm CMOS technology. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1760–1762, 2016

Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. While most analysis focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. At higher frequency of operations, of the order of few GHz, the interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from it's ideal nature. This gives rise to the shunt conductance matrices. In this paper we have considered the high frequency effects and modeled the interconnect as distributed RLCG segments to compute the interconnect power dissipation. The results obtained from SPICE simulation justify the accuracy of our model.

In this work, a fast turn-on settling low dropout regulator (LDO) with current limiter is presented. Dynamically operating the proposed current limiter using a decent current comparator protects the IC from any damage when an overload condition occurs or the output of the regulator is shorted. A novel low pass filter associated with voltage reference circuit, which provides highly filtered reference voltage and fast settling time, is implemented to minimize output noise due to voltage reference noise. The LDO with proposed low pass filter and current limiter has been implemented in a 0.6µm n-well CMOS process. The LDO dissipates 65µA quiescent current at 150mA full load condition and its output noise is 407.8nV/√Hz at 100Hz. Turn-on settling time of the LDO is 45µsec and threshold current of the current limiter is set to 230mA of output load current.

A CMOS process-insensitive voltage reference generator, which is based on the weighted sum of thermal voltage and difference of threshold voltages, is presented. The voltage reference circuit uses high VTH and regular VTH transistors and produces reference level of 422mV. The proposed technique is analyzed theoretically and its results are compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology for low-cost low-power applications. The circuit operates at minimum supply voltage of 1V with maximum drawn current of 577nA only. A temperature coefficient of 36ppm/°C is achieved with line sensitivity of 0.01%/V. The proposed reference generator exhibits PSRR of -60.34 dB and -37.09 dB at 100Hz and 1MHz, respectively.