Dynamic Threshold-Voltage MOSFET

In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3 V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behaviour of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13 µm IBM CMOS technology parameters have been used for simulation.

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary with absolute temperature) voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy. The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PPAT (proportional with absolute temperature) and PTAT/sup 2/. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the zero-order compensated voltage reference, will be replaced by a DTMOS (dynamic threshold MOS) transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 9.4 ppm/K for an extended input range 173 K < T < 423K and for a supply voltage of 2.5V and a current consumption of about 1/spl mu/A.

Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. The circuit is designed in the 0.18μm CMOS technology. The simulation results show that the amplifier has a 91dB open-loop DC gain and a unity gain-bandwidth of 111.4 kHz while operating at 0.4V supply voltage. This technique show remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair technique. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical applications.

This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction in comparison with CMOS Schmitt triggers, at the cost of a slight increase in delay. The performance characteristics of Schmitt trigger gates have been analyzed in term of power dissipation and delay using predictive Technology models at 180nm technology node for both CMOS and VTCMOS Schmitt trigger.

This paper presents an ultra-low power operational amplifier (opamp) with high gain and high common-mode rejection ratio (CMRR) in 45nm CMOS technology. It uses a bulk-driven differential pair in the input stage to facilitate low voltage design and to achieve a high input common-mode range (ICMR). In addition, the design employs an auxiliary differential pair that utilizes dynamic threshold MOS (DTMOS) technique to enhance the effective transconductance and hence achieves high gain and high unity-gain bandwidth (UGB). All the transistors are biased to operate in subthreshold region in order to minimize power consumption. Simulation with Cadence Virtuoso for 350 mV of supply and a load capacitance of 1 pF, yields a DC gain of 77.03 dB, CMRR of 130.8 dB, UGB of 456.9 kHz and a phase margin of 82.47° for a power consumption of 21.75 nW.

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

In this paper, we discuss dynamic threshold MOS (DTMOS) operations for nMOSFETs of different dielectric types and thicknesses. We found that, under the DT mode of operation, all devices exhibit a threshold voltage close to 0.7 V, independent of the thickness and gate dielectric type of the device. This is due to the diminished influence of the body effect factor. Formulations of threshold voltage and subthreshold swing of DTMOS are developed to gain insights into this unique phenomenon, and simulation of the subthreshold swing is also provided.

Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I – V and g m – V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

Self–correcting Compliant Plate Seals are being developed for various turbomachinery sealing applications including gas turbines, steam turbines, aircraft engines and oil &amp; gas compressors. These seals consist of compliant plates attached to a stator in a circumferential fashion around the rotor. The compliant plates have a slot that extends radially inwards from the seal outer diameter, and an intermediate plate extends inwards into this slot from stator. This design is capable of providing passive hydrostatic feedback forces acting on the compliant plates that balance at a small tip–clearance. Due to this self–correcting behavior, this seal is capable of providing high differential pressure capability and low leakage within a limited axial span, and robust non–contact operation even in the presence of large rotor transients. In this paper we have described the testing of Compliant Plate Seals in a static leakage test rig (“shoebox” rig) to study the impact of different design parameters on leakage and vibration. A novel high–speed visualization set–up is described and the high–speed videos demonstrate robust non–contact operation for different assembly clearances, bridge–gaps and bridge–heights, for various differential pressure and pressure ratio conditions. The reported leakage results indicate that the leakage is relatively insensitive to assembly clearances due to the self–correcting behavior.

Conventional image sensor pixel is based on amorphous silicon photodiode (PD) and amorphous silicon thin film transistor (TFT), which has complex fabrication process and low frame rate due to the low mobility of amorphous silicon. Here, we demonstrate a new type of flat panel image sensor based on low-cost two-step deposited perovskite PD arrays oxide (IGZO) TFTs. Our integrated TFT/PD system takes advantage of the low off current (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> A) of IGZO TFT and highly sensitive perovskite PD, showing a photoresponse down to 142 nW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a responsivity of 0.2 A/W, a specific detectivity of 5.7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> Jones, and a high electrical switching speed (15 ms). In addition, the system can be fabricated on flexible substrates, and the perovskite PD exhibits a significant direct X-ray response, reaching a sensitivity of ~887 μCGy <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> under 9 mGy/s irradiation. Our work of combining oxide TFT with perovskite-based PD offers an advanced strategy for developing low cost and high-performance image sensors for direct and indirect X-ray imaging applications.

In this paper, the influence of proton irradiation is experimentally studied in triple gate Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS). The drain current, transconductance and Drain Induced Barrier Lowering (DIBL) will be compared in the DT mode and the standard biasing configuration. Moreover, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance and intrinsic voltage gain will be studied. The results indicate that the DTMOS FinFET structure shows superior electrical characteristics and a better analog performance before and after irradiation.

4H silicon carbide (4H-SiC) metal-insulator- semiconductor field-effect transistors (MISFETs) with 4H aluminum nitride (4H-AlN) gate insulators have been demonstrated. The 4H-AlN layers are isopolytypically grown on 4H-SiC (1120) by molecular-beam epitaxy. Gate controlled transistor operation was realized using the AlN/SiC MISFETs. The MISFETs exhibit a low gate leakage current (<;10-10 A) and normally ON characteristics with a threshold voltage of approximately -10 V and a field-effect mobility of 0.5 cm2V-1s-1. Capacitance-voltage measurements of AlN/SiC MIS capacitors reveal a large negative flat band shift of -10.9 V, which is consistent with the normally ON characteristics.