A real-time jitter measurement board for high-performance computer and communication systems

The advancement in silicon device technology with its associated frequency increases is having a major affects across all electronic market segments. These range from basic consumer electronics to high-performance computer and communications systems. As semiconductor ground rules and densities continue to improve, the resulting smaller chips are enabling more and more function to be integrated on an individual die; thus, enabling even smaller and lower cost chips than exist today. These relatively inexpensive parts are finding their way into affordable electronic products such as personal computers, cellular telephones, and palmtop computers.

Energy efficiency for high-performance computing and communication systems has recently become an important concern, but most current grid environments do not implement energy-aware resource management. This paper proposes an energy-aware grid resource scheduling scheme. Energy-aware grid resource scheduling optimisation is formulated as utility optimisation. The goal of the paper is not only to reduce energy consumption, but also to improve the system utility in the grid environment, ensuring the battery lifetime and the deadlines of the grid applications. To reduce the computational complexity, we decompose the energy-aware grid resource scheduling optimisation problem into two sub-problems; the interaction between the two sub-problems is controlled through the use of the pricing variable. The paper proposes an energy-aware grid resource scheduling optimisation algorithm. The performance evaluation of the algorithm is conducted by comparing with other related algorithms.

The advent of serial communication links in chip-to-chip and system-to-system applications has resulted in intense focus on jitter and BER testing techniques, including jitter generation and measurement methodologies. We describe techniques for injection of random and deterministic jitter in controlled and programmable fashion, including a novel data-dependent jitter (DDJ) generation method that eliminates the need for bulky and difficult-to-control DDJ injection filters. These techniques can be employed for a wide range of applications with different bit rates and patterns in a single setup. We also introduce the concept of continuous time interval analyzer (CTIA) and demonstrate how it can be used for fast and accurate jitter measurement without any trigger signal. Subsequently, we present jitter measurement methodologies and results using the real-time and equivalent-time sampling oscilloscopes, which are used as benchmarks for verification of the CTIA measurement accuracy.

Wide area protection is the system protection against the electric power system wide area disturbance based on the modern measurement and communication technology. The three-level structure is a good structure for Wide Area Protection System (WAPS), but it relies on high-performance communication system. The purpose of this paper is to design a suitable communication network for the three-level WAPS. By analyzing the communication needs of the WAPS, the authors divide messages need to be transmitted into several sorts, and determine the demands of various messages for communication system. Based on that, the optical fiber is selected as the communication medium, and the broadband integrated service digital network based on SDH/SONET and ATM is selected as the network type. A network topology of mixed ring-star is designed. The network makes full use of the IEC 61850 based LAN in substation and power plant. Then, the protocol sets for the key message transmissions are determined. Finally, the transmissions of key messages are simulated using OPNET modeler. The simulation result satisfies the real-time and reliability demands even under the worst situation, which confirms the effectiveness of the communication system.

In the 21st-century, wireless communication and high-speed communication incorporating computation power, mobile network/Internet access capability, and consumer electronics, will become emerging technologies. To realize high-performance wireless and high-speed communication systems, system-on-chip (SoC) is becoming one of the most important technologies for future WLAN and wireless communications systems. The paper discusses the development and status of the technique first, then gives the detailed design process, especially the HW/SW codesign and verification problems. The paper gives the conclusion that the SoC technique can reduce the cost and improve the performance of WLAN, which will become more and more important with the wide use of WLAN and will drive the development of WLAN likewise.

Usually, scientific applications outlive the lifespan of the High Performance Computing (HPC) systems for which they are initially developed. The innovations in the HPC systems’ hardware and parallel programming standards drive the modernization of HPC applications so that they continue being performant. While such code modernization efforts may not be challenging for HPC experts and well-funded research groups, many domain-experts and students may find it challenging to adapt their applications for the latest HPC systems due to lack of expertise, time, and funds. The challenges of such domain-experts and students can be mitigated by providing them high-level tools for code modernization and migration. A brief overview of two such high-level tools is presented in this chapter. These tools support the code modernization and migration efforts by assisting users in parallelizing their applications and porting them to HPC systems with high-bandwidth memory. The tools are named as: Interactive Parallelization Tool (IPT) and Interactive Code Adaptation Tool (ICAT). Such high-level tools not only improve the productivity of their users and the performance of the applications but they also improve the utilization of HPC resources.

This paper introduces a new method to promote energy efficiency in computing systems. The rapidly growing demand for computational power in high-performance computing (HPC) systems is accompanied by a significant increase in energy consumption. This research investigates the many ways to minimise energy consumption in HPC systems without sacrificing computational performance. Building upon previous research we combined and refined ideas to develop an optimised approach. Our method utilises a tri-modular framework incorporating an Energy-Efficient Hardware Design, Resource Management, and Optimisation, and Server Virtualisation. The first module employs a method of designing smart energy-efficient hardware. This method incorporates leakage reduction techniques such as clock gating and sleep states. The second module uses a technique focused on optimising server software. This method is based on Dynamic Voltage and frequency scaling (DVFS) for power management in data centres. The third module is based on server virtualisation and employs software to create multiple virtual machines on a single physical server allowing for a significant reduction in energy and hardware costs. The methods used in these three modules are systematically integrated to produce a more efficient consumption of electricity. This will allow for the computing system to minimise energy consumption without compromising computational power.

In high performance computing (HPC) systems, optical network links are often utilized for the HPC networks of these systems, but they have a relatively high rate of failure compared to their electrical counterparts. Due to the high link failure rate, evaluating the impact of these failures on HPC workloads is of particular interest. We extended the Merlin network module of the Structural Simulation Toolkit (SST) in order to evaluate the impact of link failures on applications running on HPC systems which use dragonfly network topologies.We focus on dragonfly topologies as they are frequently found in HPC systems, including NERSC Cori and Edison systems.We demonstrate our changes to SST by providing a sample of performance results and routing statistics for a dragonfly network of 8,192 nodes and three HPC workloads with 1% of optical link failures. For the three motifs under consideration, we show that the impact of link failure is largely dependent on the underlying workloads running on the system.

As the size and complexity of high performance computing (HPC) systems grow in line with advancements in hardware and software technology, HPC systems increasingly suffer from performance variations due to shared resource contention as well as software- and hardware-related problems. Such performance variations can lead to failures and inefficiencies, which impact the cost and resilience of HPC systems. To minimize the impact of performance variations, one must quickly and accurately detect and diagnose the anomalies that cause the variations and take mitigating actions. However, it is difficult to identify anomalies based on the voluminous, high-dimensional, and noisy data collected by system monitoring infrastructures. This paper presents a novel machine learning based framework to automatically diagnose performance anomalies at runtime. Our framework leverages historical resource usage data to extract signatures of previously-observed anomalies. We first convert collected time series data into easy-to-compute statistical features. We then identify the features that are required to detect anomalies, and extract the signatures of these anomalies. At runtime, we use these signatures to diagnose anomalies with negligible overhead. We evaluate our framework using experiments on a real-world HPC supercomputer and demonstrate that our approach successfully identifies 98 percent of injected anomalies and consistently outperforms existing anomaly diagnosis techniques.

In recent years, several hardware accelerators have been proposed for both embedded and high-performance computing systems. Hardware accelerators nowadays become more popular for improving the performance of modern computing systems such as Machine Learning or Big Data analytics. However, the interconnects in general-purpose hardware accelerators are not well optimized to satisfy the communication demands of an application. In this work, we present an automated approach to design hardware accelerator systems with an efficient hybrid interconnect for hardware kernels driven by the detailed data communication patterns of an application. The heterogeneous interconnect includes an NoC, shared local memory, or both. Based on the quantitative data communication profile, each application is developed with a custom hybrid interconnect to achieve an optimized performance while keeping the hardware resource usage for the interconnect as low as possible. Our experimental results in an embedded system and a high-performance computing system achieve overall application speed-ups by up to 2.87× and 1.54× compared to the baseline systems, respectively. The experimental results also show that the designed systems can reduce hardware resources usage up to 33% for the embedded system and 45% for the high-performance computing system.

Wireless communication has a very important role in the day to day life for everyone. The wireless technology is growing rapidly and there is a growing demand of high performance, capacity and larger bit rate wireless communication systems which cope wireless communication services such as high speed data, video and voice signals. Multicarrier modulation scheme like OFDM provides an efficient solution to overcome this problem. In this paper a gray scale image processing is done using a LMS algorithm with wavelet based OFDM system using the QPSK modulation scheme in AWGN and Rayleigh channel in SISO environment and results are compared with the conventional adaptive FFT based OFDM system. We reconstruct our transmitted signal at receiver; in both systems by minimizing the error by adaptive filter but the computational complexity of FFT based system is more as compared to DWT based system. Results are compared in term of SNR vs BER which shows that adaptive DWT based OFDM system perform better as compared to the conventional adaptive FFT OFDM system.

Modern High Performance Computing (HPC) sys-tems are built with innovative system architectures and novel programming models to further push the speed limit of computing. The increased complexity poses challenges for performance portability and performance evaluation. The Standard Perfor-mance Evaluation Corporation (SPEC) has a long history of producing industry-standard benchmarks for modern computer systems. SPEC's newly released SPEChpc 2021 benchmark suites, developed by the High Performance Group, are a bold attempt to provide a fair and objective benchmarking tool designed for state-of-the-art HPC systems. With the support of multiple host and accelerator programming models, the suites are portable across both homogeneous and heterogeneous architectures. Different workloads are developed to fit system sizes ranging from a few compute nodes to a few hundred compute nodes. In this work we present our first experiences in performance benchmarking the new SPEChpc2021 suites and evaluate their portability and basic performance characteristics on various popular and emerging HPC architectures, including x86 CPU, NVIDIA GPU, and AMD GPU. This study provides a first-hand experience of executing the SPEChpc 2021 suites at scale on production HPC systems, discusses real-world use cases, and serves as an initial guideline for using the benchmark suites.

On high-performance computing (HPC) systems, job allocation strategies control the placement of a job among available nodes. As the placement changes a job’s communication performance, allocation can significantly affects execution times of many HPC applications. Existing allocation strategies typically make decisions based on resource limit, network topology, communication patterns, etc. However, system network performance at runtime is seldom consulted in allocation, even though it significantly affects job execution times.In this work, we demonstrate using monitoring data to improve HPC systems’ performance by proposing a NetworkData-Driven (NeDD) job allocation framework, which monitors the network performance of an HPC system at runtime and allocates resources based on both network performance and job characteristics. NeDD characterizes system network performance by collecting the network traffic statistics on each router link, and it characterizes a job’s sensitivity to network congestion by collecting Message Passing Interface (MPI) statistics. During allocation, NeDD pairs network-sensitive (network-insensitive) jobs with nodes whose parent routers have low (high) network traffic. Through experiments on a large HPC system, we demonstrate that NeDD reduces the execution time of parallel applications by 11% on average and up to 34%.

This research addresses the pressing need to optimize Python-based social science applications for high-performance computing (HPC)systems, emphasizing the combined use of task and data parallelism techniques. The paper delves into a substantial body of research,recognizing Python’s interpreted nature as a challenge for efficient social science data processing. The paper introduces a Pythonprogram that exemplifies the proposed methodology. This program uses task parallelism with multi-processing and data parallelismwith dask to optimize data processing workflows. It showcases how researchers can effectively manage large datasets and intricatecomputations on HPC systems. The research offers a comprehensive framework for optimizing Python-based social science applicationson HPC systems. It addresses the challenges of Python’s performance limitations, data-intensive processing, and memory efficiency.Incorporating insights from a rich literature survey, it equips researchers with valuable tools and strategies for enhancing the efficiencyof their social science applications in HPC environments.

Deep neural networks have recently gained tremendous interest due to their capabilities in a wide variety of application areas such as computer vision and speech recognition. Thus it is important to exploit the unprecedented power of leadership High-Performance Computing (HPC) systems for greater potential of deep learning. While much attention has been paid to leverage the latest processors and accelerators, I/O support also needs to keep up with the growth of computing power for deep neural networks. In this research, we introduce an entropy-aware I/O framework called DeepIO for large-scale deep learning on HPC systems. Its overarching goal is to coordinate the use of memory, communication, and I/O resources for efficient training of datasets. DeepIO features an I/O pipeline that utilizes several novel optimizations: RDMA (Remote Direct Memory Access)-assisted in-situ shuffling, input pipelining, and entropy-aware opportunistic ordering. In addition, we design a portable storage interface to support efficient I/O on any underlying storage system. We have implemented DeepIO as a prototype for the popular TensorFlow framework and evaluated it on a variety of different storage systems. Our evaluation shows that DeepIO delivers significantly better performance than existing memory-based storage systems.