Energy-aware grid resource scheduling: model and algorithm

The routing results of Network-on-Chip (NoC) increase energy consumption and delay. In order to overcome this issue, Energy aware task scheduling followed by dynamic job mapping concept is developed for NoC. Energy aware task scheduling algorithm allocates tasks on different elements under process and schedules the execution. Dynamic task mapping is applied to improve the performance of NoC and also to reduce both power consumption and delay in a non-preemptive network. The result of this proposed technique is more energy efficient and reduces latency.

This work presents the design and performance results of a real-time jitter measurement board for testing high-frequency clocks and data transceivers. The board targets high-volume manufacturing test to measure sinusoidal jitter tolerance and random jitter in computer and communication systems, with a substantial reduction in test cost compared to existing equipment. The board meets jitter tolerance and random jitter measurement needs and is suitable for production testing.

The advancement in silicon device technology with its associated frequency increases is having a major affects across all electronic market segments. These range from basic consumer electronics to high-performance computer and communications systems. As semiconductor ground rules and densities continue to improve, the resulting smaller chips are enabling more and more function to be integrated on an individual die; thus, enabling even smaller and lower cost chips than exist today. These relatively inexpensive parts are finding their way into affordable electronic products such as personal computers, cellular telephones, and palmtop computers.

The energy efficiency of space heaters is rated by Annual Fuel Utilization Efficiency (AFUE) governed by the Department of Energy in the United States which is a simple ratio of usable heat and fuel usage of a single heating device. It doesn't consider the overall performance of the heating system including not only the heating devices but also the characteristics of the building in different applications. The current AFUE method calculates only the energy efficiency which is thermodynamics first law efficiency. In this research, the systematic efficiency of a heating system rather than simple device efficiency has been defined and investigated. The systematic efficiency considers the overall efficiency of the whole heating system and it varies in the different applications even though with the same heating device. So it represents the performance of the system more precisely. Analytical models have been built to calculate both the systematic energy efficiency and exergy efficiency, and to evaluate the systematic energy and exergy efficiency of heating systems for direct fired and indirect fired heaters. Efficiency performances of the systems with these two types of heaters are compared. Sensitivities of input parameters for systematic energy efficiency are studied to show the impact towards systematic energy efficiency. Indoor carbon dioxide concentration level of direct fired heating system is also studied. In a case study, results show that systematic energy efficiency of indirect fired heating system is always constant at heater device efficiency which is 80\% while systematic energy efficiency of direct fired heating system varies from 40%-92% under different condition (heat loss coefficient, ambient temperature and air change requirement), indicating that simple device efficiency is not capable to evaluate the overall performance of heating system. New efficiency method such as systematic energy efficiency used in this research is needed to better describe the performance of the heating system. Results of indoor carbon dioxide level of direct fired heating system, from 1000 to 4500 PPM under different conditions, show that indoor air quality needs to be considered while using direct fired heating.

With the rapid development of supercomputers, the power consumption by large scale computer systems has become a big concern. How to reduce the power consumption is now a critical issue in designing high performance computers. Energy-aware scheduling for large scale clusters, especially the high performance heterogeneous ones, is one of the strategies for energy saving. Proposed in this paper is a novel energy-aware task scheduling algorithm (EAMM) for heterogeneous clusters, which is based on the general adaptive scheduling heuristics min-min algorithm. The algorithm is evaluated on a simulated heterogeneous cluster. The experiment results show that the new energy-aware algorithm can achieve a good time-energy trade-off and outperform the original min-min algorithm under various conditions.

Wide area protection is the system protection against the electric power system wide area disturbance based on the modern measurement and communication technology. The three-level structure is a good structure for Wide Area Protection System (WAPS), but it relies on high-performance communication system. The purpose of this paper is to design a suitable communication network for the three-level WAPS. By analyzing the communication needs of the WAPS, the authors divide messages need to be transmitted into several sorts, and determine the demands of various messages for communication system. Based on that, the optical fiber is selected as the communication medium, and the broadband integrated service digital network based on SDH/SONET and ATM is selected as the network type. A network topology of mixed ring-star is designed. The network makes full use of the IEC 61850 based LAN in substation and power plant. Then, the protocol sets for the key message transmissions are determined. Finally, the transmissions of key messages are simulated using OPNET modeler. The simulation result satisfies the real-time and reliability demands even under the worst situation, which confirms the effectiveness of the communication system.

Usually, scientific applications outlive the lifespan of the High Performance Computing (HPC) systems for which they are initially developed. The innovations in the HPC systems’ hardware and parallel programming standards drive the modernization of HPC applications so that they continue being performant. While such code modernization efforts may not be challenging for HPC experts and well-funded research groups, many domain-experts and students may find it challenging to adapt their applications for the latest HPC systems due to lack of expertise, time, and funds. The challenges of such domain-experts and students can be mitigated by providing them high-level tools for code modernization and migration. A brief overview of two such high-level tools is presented in this chapter. These tools support the code modernization and migration efforts by assisting users in parallelizing their applications and porting them to HPC systems with high-bandwidth memory. The tools are named as: Interactive Parallelization Tool (IPT) and Interactive Code Adaptation Tool (ICAT). Such high-level tools not only improve the productivity of their users and the performance of the applications but they also improve the utilization of HPC resources.

In the 21st-century, wireless communication and high-speed communication incorporating computation power, mobile network/Internet access capability, and consumer electronics, will become emerging technologies. To realize high-performance wireless and high-speed communication systems, system-on-chip (SoC) is becoming one of the most important technologies for future WLAN and wireless communications systems. The paper discusses the development and status of the technique first, then gives the detailed design process, especially the HW/SW codesign and verification problems. The paper gives the conclusion that the SoC technique can reduce the cost and improve the performance of WLAN, which will become more and more important with the wide use of WLAN and will drive the development of WLAN likewise.

Energy efficiency of the system is always paid more attention in the research of the discharge plasma’s application technology. Based on the project of ballast water treatment technology by multiphase nanosecond pulse discharge cooperated with photocatalysis, the nozzles-plate electrode was adopted, system energy and energy efficiency were investigated with different discharge factors and compared when the nozzles were coated with the titanium dioxide (TiO2) film or not. The results show that cooperating with the photocatalysis, pulsed discharge system power and energy efficiency were not significantly affected. Reactor power increases with the absolute value of the input high voltage and pulse repetition frequency and decreases with the distance between the nozzles and the plate. There are no obvious effects of the numbers of the nozzles and the air flow rate. Energy efficiency of the system increases with the absolute value of the input high voltage, firstly, then decreases. It changes inversely with the air flow rate. The energy efficiency of the system decreases with the pulsed repetition rate and the distance between the nozzles-plate. It was up to 25.7% with the input voltage of - 30 kV, and the air flow rate of 80 mL/min, pulse repetition frequency of 50 Hz and 6 nozzles- plate distance of 0.5 cm.

This study focuses on investigating energy-aware resources and designing an energy-efficient cloud architecture. It aims to optimize the decentralization model and establish migration behavior to improve IT business operations using cloud computing. Several models were evaluated for performance metrics such as physical host use, power utilization, and service level agreement (SLA) misuse. These models include smart cloud optimization for resource configuration handling (SCORCH), V-MAN, decentralized energy-aware collaborative model (DEACM), efficient energy-aware resource management model (EEARMM), and energy and power-aware dynamic migration (EPADM). To handle resource configuration efficiently, the study employed V-MAN, DEACM, EEARMM, and EPADM within the framework of smart cloud optimization. Among these models, EPADM proved to be the most effective for resource utilization through dynamic VM migration. By leveraging EPADM, the cloud system can dynamically migrate virtual machines (VMs) to optimize resource allocation and energy consumption.

In high performance computing (HPC) systems, optical network links are often utilized for the HPC networks of these systems, but they have a relatively high rate of failure compared to their electrical counterparts. Due to the high link failure rate, evaluating the impact of these failures on HPC workloads is of particular interest. We extended the Merlin network module of the Structural Simulation Toolkit (SST) in order to evaluate the impact of link failures on applications running on HPC systems which use dragonfly network topologies.We focus on dragonfly topologies as they are frequently found in HPC systems, including NERSC Cori and Edison systems.We demonstrate our changes to SST by providing a sample of performance results and routing statistics for a dragonfly network of 8,192 nodes and three HPC workloads with 1% of optical link failures. For the three motifs under consideration, we show that the impact of link failure is largely dependent on the underlying workloads running on the system.

As the size and complexity of high performance computing (HPC) systems grow in line with advancements in hardware and software technology, HPC systems increasingly suffer from performance variations due to shared resource contention as well as software- and hardware-related problems. Such performance variations can lead to failures and inefficiencies, which impact the cost and resilience of HPC systems. To minimize the impact of performance variations, one must quickly and accurately detect and diagnose the anomalies that cause the variations and take mitigating actions. However, it is difficult to identify anomalies based on the voluminous, high-dimensional, and noisy data collected by system monitoring infrastructures. This paper presents a novel machine learning based framework to automatically diagnose performance anomalies at runtime. Our framework leverages historical resource usage data to extract signatures of previously-observed anomalies. We first convert collected time series data into easy-to-compute statistical features. We then identify the features that are required to detect anomalies, and extract the signatures of these anomalies. At runtime, we use these signatures to diagnose anomalies with negligible overhead. We evaluate our framework using experiments on a real-world HPC supercomputer and demonstrate that our approach successfully identifies 98 percent of injected anomalies and consistently outperforms existing anomaly diagnosis techniques.

Although on-device video super-resolution enables high-quality live 360-degree streaming on mobile devices, existing methods often waste energy by overlooking perceived visual quality. In this paper, we present EOS, an energy-efficient on-device super-resolution system for mobile omnidirectional video (ODV) live streaming. EOS reduces energy waste by dynamically adjusting super-resolution complexity based on the predicted visual quality of super-resolved frames. This approach raises two challenges: (1) designing an adaptive inference policy that maximizes energy savings while minimizing degradation in Quality-of-Experience (QoE), and (2) developing a method to predict visual quality under the constraints of mobile ODV live streaming. To tackle these challenges, EOS introduces EOS SR and a No-Reference Up-scaling Quality Prediction scheme. EOS SR employs a device-agnostic, scalable deep neural network optimized for mobile devices, with an energy-aware scheduler that jointly selects the optimal super-resolution model and GPU frequency. The No-Reference Upscaling Quality Prediction scheme estimates visual quality across arbitrary viewpoints in real time without requiring high-resolution reference videos. Experiments on commodity smartphones show that EOS reduces average power consumption by 34.6%–49.9% compared to baseline methods, while preserving high visual quality and frame rates.

This work comprehensively investigates the design and analysis of one-port multilayer surface acoustic wave (SAW) resonators, focusing on their application in communication systems. The motivation behind this work stems from the increasing demand for high-performance communication systems with minimal signal loss. Return loss, a key parameter in evaluating signal integrity, directly impacts the efficiency and reliability of communication systems. The methodology involves a systematic design process, starting with selecting suitable materials for the multilayer structure based on their acoustic properties and compatibility with communication frequencies. The finite element simulation tool is utilized to model and simulate the SAW resonator's behaviour, allowing for precise optimization of design parameters such as layer thickness, electrode configuration, and interdigital transducer (IDT) design. Various performance metrics, including return loss, bandwidth, and quality factor, are evaluated to assess the effectiveness of the resonator in minimizing signal reflections. The results show significant improvements in return loss reduction, demonstrating the effectiveness of the proposed design approach. This work optimised the height of the electrode and found the insertion loss of the proposed device, which was-27dB. The proposed device demonstrates enhanced performance characteristics suitable for various communication system applications, including wireless networks, radar systems, and satellite communications.

This paper introduces a new method to promote energy efficiency in computing systems. The rapidly growing demand for computational power in high-performance computing (HPC) systems is accompanied by a significant increase in energy consumption. This research investigates the many ways to minimise energy consumption in HPC systems without sacrificing computational performance. Building upon previous research we combined and refined ideas to develop an optimised approach. Our method utilises a tri-modular framework incorporating an Energy-Efficient Hardware Design, Resource Management, and Optimisation, and Server Virtualisation. The first module employs a method of designing smart energy-efficient hardware. This method incorporates leakage reduction techniques such as clock gating and sleep states. The second module uses a technique focused on optimising server software. This method is based on Dynamic Voltage and frequency scaling (DVFS) for power management in data centres. The third module is based on server virtualisation and employs software to create multiple virtual machines on a single physical server allowing for a significant reduction in energy and hardware costs. The methods used in these three modules are systematically integrated to produce a more efficient consumption of electricity. This will allow for the computing system to minimise energy consumption without compromising computational power.