Energy aware scheduling and dynamic job mapping algorithm for Network-on-Chip architectures

Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally provide a local view, which considers only the neighborhood of the mapping task. This work aims to evaluate the pros and cons of static and dynamic mapping solutions. Due to the global system view, it is expected that static mapping algorithms achieve superior performance (w.r.t. latency, congestion, energy consumption). As dynamic scenarios are a trend in present MPSoC designs, the cost of dynamic mapping algorithms must be known, and directions to improve the quality of such algorithms should be provided without increasing execution time. This quantitative comparison between static and dynamic mapping algorithms is the main contribution of this work.

Directed acyclic graph (DAG) is a popular representation of an application, which includes application characteristics such as task dependencies, task execution time and inter processor communication time. Temperature and Energy aware Dynamic Level Scheduling (TEDLS) algorithm has been shown to minimize energy consumption and processor temperature while executing DAG structured applications in a heterogeneous environment with DVS enabled processors. To improve selection process of ideal processor-speed combination, this paper provides a Naive Bayesian Classifier (NBC) based scheme. Our result demonstrates an improved energy consumption resulting from lower computational overhead.

For real time applications, time slacks of a preliminary task schedule may be exploited to conserve energy. This can be accomplished by leveraging the dynamic voltage scaling (DVS) technique to slow down clock frequency of certain cores as long as the deadline is met. In this chapter, the task of fine-tuning an existing task assignment and schedule and using DVS to lower the overall energy consumption is formulated as a graph-theoretic maximum weight clique (MWC) problem. An efficient heuristic algorithm is proposed to systematically solve this problem. A unique feature of our approach is concurrently applying DVS to slow down the execution of multiple tasks to achieve better energy savings. Extensive simulations are performed to compare this proposed algorithm against leading energy-aware task scheduling algorithm and DVS algorithm. Our algorithm exhibits 22% more energy savings than the Energy Aware Scheduling (EAS) algorithm. As for energy saving in DVS process, our MWC-based method provides a 97% saving improvement over the PV-DVS algorithm.

Energy efficiency for high-performance computing and communication systems has recently become an important concern, but most current grid environments do not implement energy-aware resource management. This paper proposes an energy-aware grid resource scheduling scheme. Energy-aware grid resource scheduling optimisation is formulated as utility optimisation. The goal of the paper is not only to reduce energy consumption, but also to improve the system utility in the grid environment, ensuring the battery lifetime and the deadlines of the grid applications. To reduce the computational complexity, we decompose the energy-aware grid resource scheduling optimisation problem into two sub-problems; the interaction between the two sub-problems is controlled through the use of the pricing variable. The paper proposes an energy-aware grid resource scheduling optimisation algorithm. The performance evaluation of the algorithm is conducted by comparing with other related algorithms.

Cloud computing is growing massively in the world of information technology. As a result of which the number of servers and virtual machines is increasing day by day. It leads to huge energy consumption and carbon emission. In this regard, task scheduling has drawn the attention of cloud service providers to reduce energy consumption and increase cloud utilization. This is a crucial issue in a heterogeneous cloud environment. In this paper, energy consumption issues of cloud datacenters are addressed and an Energy-Aware Cloud Task Scheduling (EACTS) algorithm is proposed. It is taking the concept from traditional min-min, max-min, and sufferage heuristics and merge with the energy model. These heuristics are implemented on the heterogeneous cloud environment. EACTS energy model focuses on the estimation of energy consumption in cloud datacenters. The proposed algorithms estimated the makespan, cloud utilization, and energy consumption for a benchmark dataset. The experimental results obtained from EACTS algorithm provides a valid arbitration between energy efficiency and makespan. It has shown the comparison between above mentioned algorithms for various scheduling parameters.

The conventional Deep Neural Networks (DNNs) accelerator is usually designed based on array-based processing element computing. By using the array-based computation, memory access can be reduced efficiently based on a specific dataflow. However, the computing flexibility of the contemporary DNN accelerators is usually restricted because they support the monotonous computing dataflow. Hence, the computing efficiency will be degraded under the different hyperparameters of the target DNN (e.g., kernel size, layers, etc.) Because of the high flexibility and scalability of Network on Chip (NoC) interconnection, the NoC-based DNN design methodology becomes an attractive design paradigm, which reduces the design complexity of the DNN accelerator implementation. However, the current NoC-based DNN designs usually assume that the entire DNN model can be mapped to the target NoC. In this way, the area overhead will be larger with respect to the increasing DNN scale. To solve this problem, we propose a dynamic mapping algorithm, called: dense mapping. The dense mapping is used to map the neuron operations to the NoC as long as the available computing resources are enough for the neuron operations. Besides, an input sharing mechanism is proposed to reuse input data. In this way, we can not only process a DNN model on a small-scale NoC but also decrease the number of memory access by using the proposed input sharing mechanism. Compared with the related work, the proposed approaches help to reduce 60.5% number of memory access and improve 96.5% throughput due to fewer memory accesses.

With the rapid development of supercomputers, the power consumption by large scale computer systems has become a big concern. How to reduce the power consumption is now a critical issue in designing high performance computers. Energy-aware scheduling for large scale clusters, especially the high performance heterogeneous ones, is one of the strategies for energy saving. Proposed in this paper is a novel energy-aware task scheduling algorithm (EAMM) for heterogeneous clusters, which is based on the general adaptive scheduling heuristics min-min algorithm. The algorithm is evaluated on a simulated heterogeneous cluster. The experiment results show that the new energy-aware algorithm can achieve a good time-energy trade-off and outperform the original min-min algorithm under various conditions.

Wireless sensor networks (WSNs) are an attractive platform for various pervasive computing applications. A typical WSN application is composed of different tasks. In this paper, an energy-aware task scheduling method is proposed to achieve better energy consumption/performance trade-off. The proposed method exploits a true online reinforcement learning algorithm. This method is compared with the existing approaches exploiting online learning: distributed independent reinforcement learning (DIRL), reinforcement learning (RL), cooperative reinforcement learning (CRL) and exponential weight for exploration and exploitation (Exp3), in terms of tracking quality/energy consumption trade-off. Simulation results show that our proposed method outperforms existing methods for the target tracking application.

Parallel applications often rely on work stealing schedulers in combination with fine-grained tasking to achieve high performance and scalability. However, reducing the total energy consumption in the context of work stealing runtimes is still challenging, particularly when using asymmetric architectures with different types of CPU cores. A common approach for energy savings involves dynamic voltage and frequency scaling (DVFS) wherein throttling is carried out based on factors like task parallelism, stealing relations, and task criticality. This article makes the following observations: (i) leveraging DVFS on a per-task basis is impractical when using fine-grained tasking and in environments with cluster/chip-level DVFS; (ii) task moldability, wherein a single task can execute on multiple threads/cores via work-sharing, can help to reduce energy consumption; and (iii) mismatch between tasks and assigned resources (i.e., core type and number of cores) can detrimentally impact energy consumption. In this article, we propose EneRgy Aware SchedulEr (ERASE), an intra-application task scheduler on top of work stealing runtimes that aims to reduce the total energy consumption of parallel applications. It achieves energy savings by guiding scheduling decisions based on per-task energy consumption predictions of different resource configurations. In addition, ERASE is capable of adapting to both given static frequency settings and externally controlled DVFS. Overall, ERASE achieves up to 31% energy savings and improves performance by 44% on average, compared to the state-of-the-art DVFS-based schedulers.

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.

The technological trend towards smaller feature size and related implications of reduced threshold voltage and increased number of transistors pose a power management challenge. Leakage power dominates total processor power in smaller technologies. In VLIW and clustered VLIW architectures, the large number of functional units with relatively simpler issue logic contribute significantly to the overall power consumption. The underutilization of functional units (because of inherent limitations in ILP among others) causes a significant amount of this power to be consumed in the form of leakage power. Architectural schemes proposed in the past suffer from a limited program view thereby compromising a good amount of energy savings in the form of extra transitions to/from low leakage mode. Energy aware scheduling in the context of VLIW architectures has mostly focused on acyclic scheduling. In this paper, we propose a simple and integrated compiler directed scheme that obtains significant energy savings in functional units for VLIW and clustered VLIW and works equally well for both cyclic as well as acyclic scheduled regions. Our compiler directed scheme increases energy savings in functional units up to 9% and 26% in VLIW architecture and clustered VLIW architecture respectively. We provide a preliminary experimental analysis of our algorithms using the Trimaran 4.0 compiler infrastructure.

The reliance on Network-on-Chip (NoC) Multiprocessor Systems-on-Chip (NoC-MPSoC) is proliferating in modern embedded systems to satisfy the higher performance requirement of computationally extensive multimedia streaming applications. Recently, Voltage Frequency Island (VFI) based MPSoCs are deployed for data extensive applications due to their efficient energy management. High energy utilization of edge-devices in the Internet-of-Things (IoT) produces an increased carbon footprint. In this paper we develop a novel energy-aware scheduler considering tasks with conditional constraints using VFI based heterogeneous NoC-MPSoCs (VFINoC-HMPSoC) as an edge-device.. We propose a novel non liner programming based scheduling and voltage scaling approach referred to as ALI-EBAD. This performs energy-efficiently task scheduling and voltage scaling in an integrated way. The major reason for this design is that task voltage scaling helps in steering task scheduling towards an energy-efficient solution. We performed experiment on 12 real benchmarks and the results demonstrate that ALI-EBAD outperforms CATMES-Search and CA-TMES-Quick schedulers in terms of energy-efficiency. ALI-EBAD achieves an energy-efficiency of ~ 20% over CA-TMES-Search and ~ 25% over CA-TMES-Quick.

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This application- specific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design.

Networks-on-Chip (NoC) with low-radix switches forming a simple and planar topology is typically accepted as the right interconnection infrastructure for current Chip Multi Processor and high-end Multi Processor System-on-Chip. This is mainly due to its simplicity in the physical mapping on the chip. However, as the network diameter increases, latency and power consumption are increased due to the rapidly growing queuing delay in each switch do not scale with system size. In this context, topologies with high-radix switches have been recently proposed in the NoC scenario to keep message latency low when interconnecting a large number of devices. However, the use of high-radix switches present several well-known drawbacks, being the most important the scalability in area and frequency when implemented. In addition, average and maximum wire length is increased. In this paper we present a distributed crossbar NoC architecture that reduces network latency, increases network throughput significantly. For the distributed crossbar implementation trees of 2-to-1 multiplexers with arbitration and buffer capabilities are spread over the chip, avoiding the negative impact of a high radix switch degree on NoC operating frequency, and minimizing the impact of long wires. Results show that in a 64-node NoC our most aggressive distributed crossbar configuration reduces flit latency by 42% and increases throughput by 544% with respect to the low latency flattened butterfly architecture, meanwhile area is increased a 110%. A more conservative distributed crossbar configuration obtains an increment in throughput of 276.1%, latency is decreased a 29.7%, but area is also decreased by 7%.

Abstract—The reduction of energy consumption in large-scale datacenters is being accomplished through an extensive use of vir-tualization, which enables the consolidation of multiple workloads in a smaller number of machines. Nevertheless, virtualization also incurs some additional overheads (e.g. virtual machine creation and migration) that can influence what is the best consolidated configuration, and thus, they must be taken into account. In this paper, we present a dynamic job scheduling policy for power-aware resource allocation in a virtualized datacenter. Our policy tries to consolidate workloads from separate machines into a smaller number of nodes, while fulfilling the amount of hardware resources needed to preserve the quality of service of each job. This allows turning off the spare servers, thus reducing the overall datacenter power consumption. As a novelty, this policy incorporates all the virtualization overheads in the decision process. In addition, our policy is prepared to consider other important parameters for a datacenter, such as reliability or dynamic SLA enforcement, in a synergistic way with power consumption. The introduced policy is evaluated comparing it against common policies in a simulated environment that accurately models HPC jobs execution in a virtualized datacenter including power consumption modeling and obtains a power consumption reduction of 15 % with respect to typical policies. Index Terms—Virtualization, HPC, Energy, SLA, Scheduling I.