A reconfiguration solution for CMOS frequency synthesizers in cognitive radios

This article discusses the current state and development trends of microwave frequency synthesizers for test-and-measurement instruments. The discussed trends are also applicable for other synthesizer types used as modules in more complex systems. Test-and-measurement synthesizer market is estimated at $300 with an annual growth rate about 3%.A modern trend for the development of frequency synthesizers is associated with low phase noise, low spurious and fast switching speed. Important parameters also include operating frequency range, frequency resolution, modulation capabilities as well as size and cost characteristics. The main architectures based on direct analog, direct digital and indirect synthesis are evaluated. As of today, traditional indirect phase-lock-loop (PLL) architectures still dominate. On the other hand, direct analog synthesis is the most advanced approach that demonstrates extremely fast switching speed and low phase noise. Nevertheless, future developments are associated with direct digital synthesis (DDS) due to the rapid progress in solid-state technologies. DDS are currently available as special integrated circuits (IC) or can be build using field-programmable logic arrays (FPGA) and high-frequency digital-to-analog converters (DAC). Parallel (multichannel) digital structures coupled with high-frequency DACs allow generating output signals at microwave frequencies. Further improvements are possible using two or more DACs in an interleaved data mode. Wider frequency coverage through several tens of gigahertz and lower spur characteristics are expected.The article notes that modern frequency synthesizers allow generating complex signals using vector IQ-modulation. The modulation bandwidth is constantly increases through hundreds of megahertz or even several gigahertz. Further advances in microwave frequency synthesizers are associated with new reference types such as sapphire-loaded cavity oscillators with combined frequency stabilization as well as optoelectronic methods.

In this paper, a triple-controlled direct digital synthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHz frequency synthesis is presented. The architecture has the merits of low spurs, a fast switching speed and high frequency resolution. It corrects the output of DDS and changes the division ratios of two variable frequency dividers in PLL to avoid high level spurs falling in the loop bandwidth of PLL. The additional DAC output is added to the output of the loop filter to drive the VCO. It provides the PLL with a fast switching speed. Experiment and measurement results showed that this type of frequency synthesizer architecture has better performance than conventional PLL and can be used in most applications of frequency synthesis.

This paper describes a low spurious and small step frequency synthesizer module based on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-PLL structure, which is controlled by the parallel port of the computer. The module consists of four parts: the first PLL (PLL1), the DDS, the second PLL (PLL2) and the control part. The spurious of this module is ameliorated to some extent in comparison with traditional synthesizer technologies using single PLL. The experimental measurement of the actual module shows that the spurious is as low as -65 dBc. In addition, its frequency range is 2060 MHz-2160 MHz, the frequency step size 10 kHz, the phase noise -90 dBC/Hz@10 kHz and the harmonics -40 dBc.

Phase-locked loop (PLL) is applied to mass measurement using damped dynamic vibration absorber. The frequency response curves of a mass-spring system with a dynamic vibration absorber pass through a point that is independent of damping in the absorber. The measurement system utilizes this fixed point to estimate mass independently from damping. To carry out such measurement, the excitation frequency must be tuned to equal the frequency of the fixed point. For such tuning, PLL is applied. The PLL system consists of two detection circuits, a microcomputer and a direct digital synthesizer. It adjusts the excitation frequency for the phase between the excitation signal and the displacement of the absorber mass to be 180 degrees. In the experiments, the frequency responses are measured to confirm the existence of the fixed point. The automatic tuning is achieved by the developed system. Mass measurements are carried out in the developed apparatus. The results demonstrate the efficacy of the measurement using PLL and that the measurement utilizing the fixed point is insensitive to the damping in the absorber.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

A 77-GHz synthesizer consisting of a phase locked loop (PLL) and a direct digital synthesizer (DDS) optimised for the application in frequency modulated continuous wave (FMCW) radars is presented. Through extensive noise shaping, the DDS uses a very small lookup table for storage of the sine function values and requires a digital-analog converter (DAC) with only 6 bit resolution. The design achieves high clock rates via the use of parallelisation.

This paper updates results of our work on gas spectroscopy based on transmitters (TXs) and receivers (RXs) in IHP's 0.13 μm SiGe BiCMOS technology. The improved performance of our system is shown by the absorption spectra of gaseous methanol in the range 241 - 242 GHz at 1.4 Pa, corresponding to an absorption line width of about 1 MHz. The signal-noise ratio (SNR) for the absorption line of methanol at 241.7 GHz is used as measure. The system includes two fractional-n phase-locked loops (PLLs), which allow frequency ramps for the TX and RX, and a superimposed frequency shift keying modulation (FSK) for the TX. Another option includes reference frequency ramps for the PLLs in integer-n mode, which are realized by a direct digital synthesizer (DDS). An SNR of 1515 is observed for the 241.7 GHz absorption line at 1.4 Pa. We extend our single band TX/RX system with the range 238 - 252 GHz to a multi-band system to cover the range 225 - 273 GHz. It is built by combining corresponding pairs of TXs and RXs of three frequency bands in this range. The multi-band operation allows parallel spectra acquisition for these bands. For the TXs and RXs appropriate frequency ramps are generated by their external fractional-n PLL devices.

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

The non-linear nature of charge versus polarization in ferroelectric capacitors offers the unique opportunity to minimize jitter in phase locked loops (PLL). During the low effective capacitance state, the clock generation signal within the PLL has a high slew rate offering excellent timing characteristics. During the rest of the clock period, the high effective capacitance state is used to average inherent PLL noise. In this paper, we present the improved jitter that results when a PLL is implemented utilizing a strontium bismuth tantalate niobate based ferroelectric capacitor compared to conventional linear capacitor. In addition, we present the analysis of jitter in terms of capacitance characteristics of ferroelectric capacitor. When integrated on CMOS technology, PLLs based on ferroelectric capacitors have great potential for producing reduced jitter clock sources usable in future clock recovery and communication circuits.

A frequency synthesizer based on SIP Technology with novel structure is presented in this paper, which combines the advantages of miniaturization and easy to maintain. The system is designed on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-MIX (Mixer), implemented in LTCC and Fuzz-Button. According to that, an excellent performance Ku-Band (14.6GHz~14.8GHz) frequency synthesizer SIP with low phase noise (<; -95dBc/Hz@1kHz) and low spurious in narrow band (<; -75dBc) is developed. Using this structure, the size of frequency synthesizer is reduced to 31.8x40.6x6mm.

Phase locked loops (PLLs) are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid Electromagnetic Interference (EMI). Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow (Fig. 1 (a)). That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) is needed to obtain smaller output frequency steps than reference frequency. It is important to make Frac-N PLLs as soon as possible to meet a market opportunity. However, it takes long time to make them from scratch. One of answers would be Frac-N digital PLL whose most part is digital circuit which is quickly designed with RTL. However, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [1], [2]. The TDC is a key analog block that requires long time to design and calibration which increases complexity. If we have a fractional divider (FDIV) to make a Frac-N PLL by just connecting to an Int-N PLL, it is useful. Some Frac-N PLLs [3], [4] have been published and they have FDIVs. In [3], extra coarse frequency control is needed to generate the frequency information, increasing complexity. In [4], two-step phase interpolation has been proposed to reduce $\Delta \sum$ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector. It is tough to apply this structure to ordinary PLLs.

A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.

Linearly frequency modulated (LFM) signals are desired in many electronic systems. For example, linearly frequency modulated continuous wave (LFMCW) radar has the good performance of lightweight, cost-effective, and high-resolution imaging. However, the presence of frequency nonlinearity in the transmitted signal will result in contrastand range-resolution degradation. In this paper, the impact of frequency nonlinearities on LFMCW synthetic aperture radar (SAR) system is addressed, and one parallel direct digital synthesizer (DDS)-driven phase locked loop (PLL) frequency synthesizer to synthesize wideband LFM signals is designed, and an adaptive system nonlinearity compensation technique is employed. In this way, an example wideband LFM synthesizer with good performance frequency linearity is designed.

A 29.5 to 31.7 GHz fully integrated phase locked loop (PLL) is presented in this paper. An integrated voltage-controlled oscillator (VCO) and a set of high-speed dividers are used to accomplish all the frequencies. The shunt peaking inductors is added in the first CML divider to higher the operating frequency and lower the power consumption. The current steering charge pump is utilized to improve switching time and thus allow high-speed operation. The PLL can be locked from 29.5 to 31.7 GHz. The PLL including buffers consumes 48mW from 1.2/0.7 V supplies. The output spectrum shows spur suppression higher than 23 dBc. Fabricated in a 65 nm CMOS process, the PLL occupies a chip area of 1.44 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper proposed a versatile signal generator which employed a phase lock loop (PLL) chip and a direct digital synthesizer (DDS) chip to produce microwave signal for 3G mobile communication jamming. Based on the self-developed software, it could be controlled to produce single frequency, amplitude modulation (AM), frequency shift keying (FSK) or binary phase shift keying (BPSK) signal for different effective jamming applications. For different configuration or small changes, it could be used for other applications. Spectrum and infield tests demonstrated the jamming signals.