JITTER ANALYSIS AND PREDICTION FOR PHASE LOCKED LOOPS UTILIZING FERROELECTRIC CAPACITORS

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

The reduction of timing jitter has become a primary goal in the design of Phase Locked Loops (PLLs) and Delay Locked loops (DLLs) for high data rate systems. Timing jitter causes a decrease in timing margin and reduces the maximum achievable frequency of operation for digital circuits. This paper proposes a capacitor compensation scheme to reduce accumulated jitter in PLLs. The focus of this investigation is on the reduction of power supply induced noise to the Voltage Controlled Oscillator (VCO). For a 250MHz PLL designed in 0.13um CMOS technology the long term accumulated jitter was simulated at 1.3ns peak to peak which reduced to 750ps peak to peak after the addition of our compensation scheme.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed technique can be applied to PLLs whose jitter is predominantly due to power supply noise. Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the supply voltage to the PLL and noting that PLL jitter is extremely sensitive to power supply variations, it is possible to introduce significant jitter into the PLL output which can be measured using a low-cost tester During production test, a regression model is used to predict the inherent PLL jitter from the measurement of power supply induced jitter.

A nonvolatile SRAM has been designed and fabricated by integrating with ferroelectric HfO2 capacitors, and its store/recall operation before/after power-off have been experimentally demonstrated. Excellent ferroelectricity and memory characteristics have been obtained in sub-10nm-thick ferroelectric HfO2 capacitor. The NVSRAM with ferroelectric HfO2 capacitor can be a candidate for cost-effective, normally-off and ultralow power embedded memory solution for IoT power management. Introduction IoT edge devices have been playing key roles as sensor node device. The number of IoT edge devices is predicted to be trillions or even more, and then obviously the device must operate at ultralow power in the order of 1mW or less [1]. IoT edge device operates in an intermittent mode where the switching times of a transistor per second is very small in average. Then the power consumption is dominated by standby leakage current especially in high capacity memory such as SRAM. Therefore it is very important to suppress leakage current of a memory cell. One possible approach is to turn off power supply for memory cells. To do so, state information must be stored and recalled, before and after power-off, so that latency and power overhead are mitigated. This is so called normally-off computing and low power nonvolatile memory needs to be integrated to SRAM, which turns out to be nonvolatile SRAM (NVSRAM) [2-4]. There are several architectures for NVSRAM. Ferroelectric NVSRAM has an advantage of low voltage and low power operation [4]. However, conventional ferroelectric material has several issues in CMOS compatibility and scaling. Recently, ferroelectricity has been discovered in HfO2 thin film which is already used in CMOS process as a high-k dielectric [5-7]. Ferroelectric HfO2 opens new paths for ferroelectric-based low power devices including NVSRAM. In this paper, NVSRAM is designed and fabricated by integrating ferroelectric HfO2 in our university lab. We focus on functional device implementation as a proof-of-concept for normally-off computing and IoT power management. Device Operation and Design Consideration In this work, among several ferroelectric NVSRAM architectures [4,8-11], we chose 6T-2C NVSRAM architectures (Fig.1) [4] because of its simple structure, operation principle, and above all its simple process integration with ferroelectric HfO2 capacitor. NVSRAM cell is made of 6T SRAM cell and two ferroelectric capacitors at the SRAM nodes. Bottom electrodes of ferroelectric capacitors are connected to plate line (PL). NVSRAM operates just as normal SRAM with PL is VDD/2. It only needs to flip ferroelectric polarization during store operation before power-off, which mitigates reliability requirement of ferroelectric capacitors. One of the most critical operations is recall. The nodes have opposite polarizations and thus different capacitances. The recall operation makes use of this capacitance imbalance to regenerate node voltages. Capacitor size and voltage ramp rate need to be carefully chosen. We confirmed recall operation in our NVSRAM design by SPICE simulation which was calibrated by our MOSFET and MIM capacitor. Experiments and Discussions NVSRAM was fabricated by following process flow. First SRAM was fabricated by conventional SOI CMOS process. After contact formation, bottom TiN/Ti electrode was deposited by sputtering. Then HfO2 doped with Zr was deposited by ALD system, followed by top TiN electrode deposition by sputtering. MIMS capacitor was formed by simple subtractive etching process. Lastly, RTA was performed to crystalize the HfO2 film. Fig. 2 shows the cross sectional TEM image of the ferroelectric HfO2 capacitor, where we confirmed uniformly crystallized 9nm-thick HfO2 thin film. PV characteristics of the MIM capacitor integrated on SRAM cell does not show any degradation as shown in Fig. 3. We also confirmed sufficient capacitance difference for each polarization state. From retention measurement, more than 1 year retention is estimated. Measured endurance cycle was 1x108 which is close to requirement for IoT power management, 1x109. NVSRAM cell shows no difference in static SRAM butterfly curve from reference SRAM cell on the same chip. Fig. 4 shows the measured waveform of the entire NVSRAM operation. First, data was written in normal SRAM mode, and then store operation was performed before power-off. After arbitrary sleep time, recall operation was performed and the written data was verified. We confirmed correct store and recall operation in NVSRAM and demonstrated nonvolatile functionality with ferroelectric HfO2 capacitors. Summary We experimentally demonstrated the nonvolatile functionality of the NVSRAM integrated with ferroelectric HfO2 capacitor fabricated in the university lab. NVSRAM will enable normally-off computing for IoT power management at low cost. In this work, we focused on demonstrating essential store/recall operations. Design optimization for high density and high speed operation using relevant CMOS technology will be our future work. Figure 1

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

This article proposes a reconfiguration solution for CMOS frequency synthesizer with a hybrid architecture which is a combination of a Direct Digital Synthesizer (DDS) and a Phase Locked Loop (PLL). The DDS is implemented in FPGA platform functioning a reference frequency to the PLL. The PLL is designed using CMOS technology, being reconfigurable to accelerate tuning speed. Instead of employing a hardware-based lock detector, a software algorithm is used to determine the switching time and to optimize the frequency tuning speed, consuming energy or limited pick power. This PLL is used in cognitive radio for spectrum sensing function.

A 29.5 to 31.7 GHz fully integrated phase locked loop (PLL) is presented in this paper. An integrated voltage-controlled oscillator (VCO) and a set of high-speed dividers are used to accomplish all the frequencies. The shunt peaking inductors is added in the first CML divider to higher the operating frequency and lower the power consumption. The current steering charge pump is utilized to improve switching time and thus allow high-speed operation. The PLL can be locked from 29.5 to 31.7 GHz. The PLL including buffers consumes 48mW from 1.2/0.7 V supplies. The output spectrum shows spur suppression higher than 23 dBc. Fabricated in a 65 nm CMOS process, the PLL occupies a chip area of 1.44 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

In this paper, we present the concept and design of a time-to-voltage converter (TVC), and demonstrate its application to on-chip phase-locked loop (PLL) jitter measurement. The TVC operates in an analog, continuous mode without using a sampling clock. It compares the signal under measurement with a reference signal by charging and discharging a capacitor. First, the low-frequency reference signal charges the capacitor in one cycle. Then, the jitter signal discharges the same capacitor repeatedly until the voltage on the capacitor falls below a threshold. The number of times the jitter signal needs to discharge the capacitor is recorded on a binary counter. We demonstrated that a 160-ps injected jitter is successfully measured by the proposed TVC with a 2-MHz reference signal. We also demonstrated the successful measurement of a 14-ps average PLL jitter, without jitter injection. An 8% measurement error is found in both experiments, using four-bit counters. Finally, we analyze the relations between design parameters and show trade-offs between measurement resolution and measurement time.

A CMOS PLL (phase-locked loop) system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is designed for use as a generic building block with large-scale CMOS video signal processing integrated circuits. The development of a custom test chip version of the PLL system is reported. A test chip version of the PLL system has been fabricated in 0.8 mu m CMOS technology and tested to verify functionality and examine acquisition and racking behavior. The test chip version of the PLL includes a bidirectional test bus monitor system used to observe 28 signals and input five signals for the purpose of assessing circuit operation details. The open-loop measured noise bandwidth of the RC VCO (voltage-controlled oscillator) is -30 dB at 350 Hz. The short term stability within one second is approximately +or-150 Hz or 20 p.p.m., corresponding to 1.3 ns jitter in one horizontal line period of 63.5 mu s. >

Phase-locked loop (PLL) based clock and data recovery (CDR) circuits use a 2x-oversampling (2XO) of the incoming non-return to zero (NRZ) data stream to recover the data. As an extension of the idea, 3x-oversampling (3XO) CDR circuits provide improved performance in the presence of total asymmetric jitter. This paper presents an overview of the oversampling CDR circuits with an emphasis on digital architectures. These include, but are not limited to, the 3XO jitter-tolerant variable-interval 3XO architecture, the 3XO eye-tracking architecture, and the blind oversampling architecture. We propose a modified architecture that utilizes multiple rotating phases to improve the performance of the 3XO eye-tracking architecture

An integer-N phase-locked loop (PLL) is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a complementary crossed-couple LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a fiber lasers application in microwave signal generation and intelligent computing from a free running mode-locked Er-fiber laser. In the stretched-pulse regime, the Er-fiber laser is designed at close-to-zero dispersion to minimize the phase noise of extracted microwaves. In order to suppress the excess phase noise in the optical to electronic conversion process, we synchronize a low-noise PLL to the fiber laser using a fiber Sagnac-loop-based optical-microwave phase detector.

In this paper, a hybrid phase and frequency detector (PFD) for phase-locked loop (PLL) based clock and data recovery (CDR) applications is presented. The PFD starts the phase detection process in a binary mode, for a faster acquisition time and a higher pull in range, and after the binary PLL locks, the PD switches to the linear mode of operation resulting in a lower output jitter. The frequency acquisition range of the presented PFD is significant and it virtually can handle any data frequency. The data frequency can however be as high as the clock frequency. In all simulations of the PLL, the pull-in range of the PLL is limited by the tuning range of the voltage-controlled oscillator (VCO). A prototype PLL is designed in a 0.13 µm CMOS technology and has a lock range from 8.3 to 9.6 GHz, peak-to-peak jitter of 0.1 UI, and a worst-case lock time of 30 ns. The PLL consumes 36 mW from a 1.2 V supply.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.