Low-cost jitter measurement technique for phase-locked loops

The non-linear nature of charge versus polarization in ferroelectric capacitors offers the unique opportunity to minimize jitter in phase locked loops (PLL). During the low effective capacitance state, the clock generation signal within the PLL has a high slew rate offering excellent timing characteristics. During the rest of the clock period, the high effective capacitance state is used to average inherent PLL noise. In this paper, we present the improved jitter that results when a PLL is implemented utilizing a strontium bismuth tantalate niobate based ferroelectric capacitor compared to conventional linear capacitor. In addition, we present the analysis of jitter in terms of capacitance characteristics of ferroelectric capacitor. When integrated on CMOS technology, PLLs based on ferroelectric capacitors have great potential for producing reduced jitter clock sources usable in future clock recovery and communication circuits.

The reduction of timing jitter has become a primary goal in the design of Phase Locked Loops (PLLs) and Delay Locked loops (DLLs) for high data rate systems. Timing jitter causes a decrease in timing margin and reduces the maximum achievable frequency of operation for digital circuits. This paper proposes a capacitor compensation scheme to reduce accumulated jitter in PLLs. The focus of this investigation is on the reduction of power supply induced noise to the Voltage Controlled Oscillator (VCO). For a 250MHz PLL designed in 0.13um CMOS technology the long term accumulated jitter was simulated at 1.3ns peak to peak which reduced to 750ps peak to peak after the addition of our compensation scheme.

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

For a Phase-Locked Loop (PLL), the clock period variation is one important health condition indicator. In this paper, we present a rapid min-MAX period monitoring scheme for PLLs, using circuits made of only standard cells. The proposed scheme can monitor the clock period of a PLL 's output clock signal continuously during a designated monitoring session, while reporting the minimum and maximum clock periods in a timely manner. As a result, performance hazards can be timely exposed and an alarm can be raised earlier. The most unique contribution in this work is the design of a novel min-MAX Time-to-Digital converter (TDC). We have implemented this monitoring scheme and integrated it with a cell-based PLL in a 90nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that the proposed scheme is able to detect some dangerous conditions when the PLL 's output clock signal exhibits abnormal clock cycle times due to some online transient fault.

In this paper, an improved algorithm for realizing a phase locked loop (PLL) for three phase system is reported. The reported approach results in fast dynamic response and negligible distortion in PLL output, under severely distorted utility conditions, even with appreciable DC offset in input signals. Also, the locking time obtained is independent of the level of utility distortion. So this PLL is eminently suitable for decoupled control of active and reactive power in all custom power devices, including dynamic voltage restorer (DVR). Important design details are provided which are supported with simulation results. These are experimentally verified and compared with existing methods to highlight the improvements.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190ps rms , has reference spur of −59.5dB, occupies 0.0175mm2 area and consumes 600µW power. The PLL has an FOM of −196.6dB.

In this paper, we present the concept and design of a time-to-voltage converter (TVC), and demonstrate its application to on-chip phase-locked loop (PLL) jitter measurement. The TVC operates in an analog, continuous mode without using a sampling clock. It compares the signal under measurement with a reference signal by charging and discharging a capacitor. First, the low-frequency reference signal charges the capacitor in one cycle. Then, the jitter signal discharges the same capacitor repeatedly until the voltage on the capacitor falls below a threshold. The number of times the jitter signal needs to discharge the capacitor is recorded on a binary counter. We demonstrated that a 160-ps injected jitter is successfully measured by the proposed TVC with a 2-MHz reference signal. We also demonstrated the successful measurement of a 14-ps average PLL jitter, without jitter injection. An 8% measurement error is found in both experiments, using four-bit counters. Finally, we analyze the relations between design parameters and show trade-offs between measurement resolution and measurement time.

Direction finding techniques can be applied to a number of military and civilian systems, such as radar, sonar, and radio communications. It aims at finding the Direction of Arrival of an electromagnetic source for positioning purposes. Direction finding systems can be primarily classified as multiple or single channel. The single-channel solution, investigated herein, is based on a switched antenna associated to a special Phase Locked Loop (PLL) receiver architecture that allows tracking the phase of each antenna. The PLL output is processed by a signal processing block that removes the ambiguity inherent to the PLL and estimates the angle of arrival of the source. This procedure is usually linked to high computational complexity that increases with the number of antennas and with the modulation level. This article proposes a technique to decrease the computational burden of the PLL-based single receiver DOA estimation scheme and to use the super resolution algorithm Multiple Emitter Location and Signal Parameter Estimation to obtain azimuth and zenith angles with improved accuracy. The simulated results using the novel algorithm are shown and its performance compared to the traditional solution in different scenarios.

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

The paper describes the design procedure of phase-locked loop (PLL). This PLL is used in measurement chain with pressure sensor and band-pass sigma-delta modulator to synchronize the input slow sine-wave signal from sensor with driving clock (signal from PLL) of modulator. The frequency of input sine-wave signal is 15,625 kHz. The PLL output (voltage controlled-oscillator) has to generate 62,5 kHz square driving signal. The paper shows design process of most important stages in CMOS 0.7 mum AMIS technology and it also presents simulation results, which confirm the design process of these blocks.

Current control in three-phase voltage source converters (VSC) is usually performed in the dq-coordinate system because of its ability to eliminate steady-state tracking errors. For grid-connected VSCs, such as PWM rectifiers and grid-parallel inverters for integration of renewable energy and energy storage devices, a phase-locked loop (PLL) is commonly used to synthesize a set of harmonic-free voltages synchronized to the grid voltages for transformation between the dq and the abc coordinate systems. The multitude of control functions in large systems, such as wind turbines, necessitate the use of multiple digital control devices. In such cases, the PLL output has to be transferred among different devices. To reduce the bandwidth requirements and noise susceptibility of such signal transfer, this paper presents a PLL implementation method that distributes the PLL function into different devices. Instead of transferring directly the synthesized grid voltage angle, the synthesized grid frequency, which has much lower signal bandwidth, is communicated. A binary reset signal is used to eliminate the difference between initial values of the distributed integrators that convert locally frequency into reference angle. An experimental system consisting of a three-phase VSC, a TMS320F28335 DSP, and an Altera DE2 board with a Cyclone II EP2C35 field programmable gate array (FPGA) is used to demonstrate the proposed concept.

Peripheral sensory activity follows the temporal structure of input signals. Central sensory processing uses also rate coding, and motor outputs appear to be primarily encoded by rate. I propose here a simple, efficient structure, converting temporal coding to rate coding by neuronal phase-locked loops (PLL). The simplest form of a PLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate, the further the local oscillator is driven from its intrinsic frequency. Sequences of input intervals, which by definition encode input information, are thus represented by sequences of firing rates at the PLL's output. The most plausible implementation of PLL circuits is by thalamocortical loops in which populations of thalamic "relay" neurons function as phase detectors that compare the timings of cortical oscillators and sensory signals. The output in this case is encoded by the thalamic population rate. This article presents and analyzes the algorithmic and the implementation levels of the proposed PLL model and describes the implementation of the PLL model to the primate tactile system.

Fractional- N phase-locked loops (PLLs) typically use noise-shaping coarse quantizers to control their instantaneous output frequency. The resulting quantization noise and its running sum inevitably get distorted by non-ideal analog components within the PLL, which induces undesirable spurious tones in the PLL's output signal. A recently proposed quantizer, called a successive requantizer, has been shown to mitigate this problem. Its quantization noise and the running sum of its quantization noise can be subjected to up to fifth-order and third-order nonlinear distortion, respectively, without inducing spurious tones. This paper extends the previously published successive requantizer results to enable the design of successive requantizers whose quantization noise running sum sequences attain such immunity to nonlinearity-induced spurious tones up to arbitrarily high orders of distortion. The extended results are used to design example successive requantizers whose quantization noise and quantization noise running sum sequences have optimally reduced susceptibility to nonlinearity-induced spurious tones.