Improved PLL Under Distorted Utility Conditions

This paper proposes a decoupled power control algorithm for grid integration of photovoltaic (PV) systems using quasi-Z-source inverter (qZSI). The proposed controller uses model predictive control (MPC) framework to inject the maximum available power harvested from the PV panels to the grid and also to compensate reactive power required by the grid. Thus, a power electronics interface (PEI) is proposed to integrate the PV panels to the grid and also to work as a reactive power compensator simultaneously. A reliable technique is proposed to regulate the impedance network elements' voltage and current according to the maximum operating point of PV panels and grid voltage/current requirements. The proposed controller features simple structure for practical implementation, fast dynamic response under changing sky condition, and negligible tracking error in steady state condition for decoupled active and reactive power control in a typical distributed generation (DG) systems. The performance of the proposed controller is verified experimentally using dSPACE-DS1007 platform, and the grid-side power quality analysis is provided and evaluated according to IEEE-519 standard.

For a Phase-Locked Loop (PLL), the clock period variation is one important health condition indicator. In this paper, we present a rapid min-MAX period monitoring scheme for PLLs, using circuits made of only standard cells. The proposed scheme can monitor the clock period of a PLL 's output clock signal continuously during a designated monitoring session, while reporting the minimum and maximum clock periods in a timely manner. As a result, performance hazards can be timely exposed and an alarm can be raised earlier. The most unique contribution in this work is the design of a novel min-MAX Time-to-Digital converter (TDC). We have implemented this monitoring scheme and integrated it with a cell-based PLL in a 90nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that the proposed scheme is able to detect some dangerous conditions when the PLL 's output clock signal exhibits abnormal clock cycle times due to some online transient fault.

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

This paper introduces a simple and effective control algorithm for generation of reference voltages based on Three-phase dual SO-SOGI (Second Order-Second Order Generalized Integrator) based Phase Locked Loop (PLL) for DVR (Dynamic Voltage Restorer). The proposed DVR scheme is implemented to achieve faster compensation of voltage sag, swell with and without phase jump and at harmonic conditions. Three-phase PLL is used to extract the phase information and amplitude to control and to inject the required voltage at the load end. The SO-SOGI based QSG (Quadrature Signal Generation) and PLL are found effective in mitigating inter-harmonics, harmonics, DC-Offset and unbalance in the estimated parameters. This enables the DVR with the proposed control algorithm to inject reference voltage accurately under linear/ non-linear load conditions. In this paper, SO-SOGI is chosen because of its dynamic response, tracking accuracy and faster detection under all varying grid conditions within a very short duration of time. The control algorithm is tested and evaluated using MATLAB/Simulink and has proved its effectiveness.

Dynamic voltage restorers (DVRs) are used to protect sensitive loads from the effects of voltage sags on the distribution feeder. This paper presents and verifies a novel voltage sag detection technique for use in conjunction with the main control system of a DVR. In all cases it is necessary for the DVR control system to not only detect the start and end of a voltage sag but also to determine the sag depth and any associated phase shift. The DVR, which is placed in series with a sensitive load, must be able to respond quickly to a voltage sag if end users of sensitive equipment are to experience no voltage sags. A problem arises when fast evaluation of the sag depth and phase shift is required, as this information is normally embedded within the core of a main DVR control scheme and is not readily available to either users monitoring the state of the grid or parallel controllers. Previous research presented an additional controller, which required phase and sag depth information to manipulate the injection voltage vector returned by the main controller in order to prevent the DVR injection transformers from saturating. Typical standard information tracking or detection methods such as the Fourier transform or phase-locked loop (PLL) are too slow in returning this information, when either applied to the injection voltage vector, or to the supply voltages directly. As a result of this the voltage sag detection method in this paper proposes a new matrix method, which is able to compute the phase shift and voltage reduction of the supply voltage much quicker than the Fourier transform or a PLL. The paper also illustrates that the matrix method returns results that can be directly interpreted, whereas other methods such as the wavelet transform return results that can be difficult to interpret.

A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed technique can be applied to PLLs whose jitter is predominantly due to power supply noise. Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the supply voltage to the PLL and noting that PLL jitter is extremely sensitive to power supply variations, it is possible to introduce significant jitter into the PLL output which can be measured using a low-cost tester During production test, a regression model is used to predict the inherent PLL jitter from the measurement of power supply induced jitter.

A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190ps rms , has reference spur of −59.5dB, occupies 0.0175mm2 area and consumes 600µW power. The PLL has an FOM of −196.6dB.

The continuity of supply and quality of power supplied to the customers must be uninterrupted from the reliability point of view. The Dynamic Voltage Restorer (DVR) is a custom power device which has an advantage of fast dynamic response and can generate real or reactive power independently. This paper presents the improved topology for DVR by the integration of Proton Exchange Membrane Fuel Cell (PEMFC) with boost converter as a DC input to the DVR. Thus the proposed DVR ensures a constant DCvoltage across the DC link during the process of voltage compensation with active power injection to the grid. The performance of the proposed work is endorsed by comparing the results with conventional DVR and the simulation results are also validated to prove the effectiveness of the proposed work.

Direction finding techniques can be applied to a number of military and civilian systems, such as radar, sonar, and radio communications. It aims at finding the Direction of Arrival of an electromagnetic source for positioning purposes. Direction finding systems can be primarily classified as multiple or single channel. The single-channel solution, investigated herein, is based on a switched antenna associated to a special Phase Locked Loop (PLL) receiver architecture that allows tracking the phase of each antenna. The PLL output is processed by a signal processing block that removes the ambiguity inherent to the PLL and estimates the angle of arrival of the source. This procedure is usually linked to high computational complexity that increases with the number of antennas and with the modulation level. This article proposes a technique to decrease the computational burden of the PLL-based single receiver DOA estimation scheme and to use the super resolution algorithm Multiple Emitter Location and Signal Parameter Estimation to obtain azimuth and zenith angles with improved accuracy. The simulated results using the novel algorithm are shown and its performance compared to the traditional solution in different scenarios.

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

Power quality (PQ) is an important issue in power systems that reflects a measure of quality of energy supply to the consumers. Power electronics-based equipment is increasing in power systems that cause voltage distortions which may damage a sensitive appliance in the distribution grid. Besides, many electrical and electronic equipment is susceptible to power supply disturbances in modern industrial establishments. The most vital power quality issues affecting large commercial and industrial customers are momentary power interruptions and voltage sags. Usually, these PQ issues are associated with the faults that occur in the supplying power systems. Voltage sags are very common since they can be associated with the faults that happen remotely to the customer. Further, these PQ problems with about 4–5 cycles may cause an extensive malfunction to the sensitive equipment. Therefore, an appropriate solution is necessary to handle this problem. A Dynamic voltage restorer (DVR) is a custom power device (CPD) that can protect sensitive equipment against voltage disturbances and improve power quality in electrical distribution systems. In recent years, many CPDs have been developed to meet the need of the industries and their critical load establishment. The DVR is one of the most promising CPDs used to improve the power quality before feeding it to the sensitive load to protect electric appliances from damage. DVR is the combination of a voltage source inverter (VSI), which can impose the voltage in series through a series injection transformer (SIT) with the power distribution system during voltage sag. The required voltage compensation can be achieved by adopting the pulse width modulation (PWM) technique for VSI. The DVR's performance mainly depends upon the control system that includes voltage disturbance detection, reference generation, voltage & current control and PWM switching strategy. The main objective of the control system is to compensate for the disturbance at the earliest using a fast detection technique, optimum control variables for the control circuit and a suitable PWM switching methodology. Many such compensation methods and control techniques are proposed in the literature along with various DVR topologies which are analysed and studied in this chapter.KeywordsPower qualityDynamic voltage restorerVoltage source inverterPI controllerHarris hawk’s optimization (HHO) algorithm

In this paper, a flexible power dispatch strategy based on the elliptical trajectory is proposed to maximize the operating region for dynamic voltage restorer (DVR) during voltage sags. This control scheme introduces two individual parameters to accomplish continuous power delivery within the voltage security boundaries required by the loads. These two key parameters are presented in the exact mathematical equations of instantaneous power dispatch, which allows the individual control of active power and reactive power of DVR. Under the provisions of the given control strategy, the load voltage regulation and flexible power dispatch are combined together by the voltage sag compensation of the elliptical trajectory. Thus, the voltage source converters output current can be limited within the maximum rated value. A smooth transition can be achieved as well during changes in the operation scheme when fulfilling the presented power delivery. Eight scenarios of different active and reactive power delivery are presented to validate the feasibility of the proposed strategy. Finally, laboratory results are used to reveal the effectiveness of the given control schemes.

This paper presents a detailed analysis of PLL structures for utility connected systems. The three-phase PLL (phase-locked loop) structure capable of fast tracking the utility voltage vector is studied. A single-phase PLL structure, derived from the three-phase PLL topology, is discussed and its behavior under distorted utility conditions is analyzed. Additionally, the conventional zero-crossing PLL is studied and an alternative implementation for this PLL is proposed in order to improve its dynamic behavior. Simulation and experimental results from a DSP-based system are included to support the theoretical analysis.

The dynamic voltage restorer (DVR), a custom power device, has been proposed to mitigate voltage sags, thereby protecting sensitive loads. The maximum amount of real power that the DVR can provide to the load is a deciding factor in determining the capability of the restorer. This paper proposes a concept of interline dynamic voltage restoration (IDVR) in which several DVRs in different feeders are connected to a common DC-link energy storage. The cost of installation of a group of DVRs protecting various parts of a power system can be reduced by the sharing of a common energy storage system. While one of the DVRs carries out voltage compensation during sags, the other DVRs can replenish energy to the DC-link to maintain the DC-link voltage at a specific level. A closed-loop controller that consists of an inner current loop and an outer voltage loop is incorporated into the IDVR system in both the voltage control and the power flow control modes. Simulation results are presented to verify the efficacy of the proposed IDVR design.

The dynamic voltage restorer (DVR) is one of the modern devices used in distribution systems to protect consumers against sudden changes in voltage amplitude. It is a custom power device used in power distribution networks to protect consumers from sudden sags (and swells) in grid voltage. Implemented at medium voltage level, the DVR can be used to protect a group of medium voltage or low voltage consumers. In this paper, the controller using the P+Resonant controller and charge regulator is proposed in order to eliminate the steady-state error in DVR response and to stabilize the system, respectively. The current limitation will restore the point of common coupling (PCC) voltage and protect the DVR itself. The innovation here is that the DVR with the fifteen level inverter systems protects the PCC voltage during a voltage sag condition without any real power injection into the DVR. Simulation results show the capability of the DVR to control the emergency conditions of the distribution systems.