Long-term jitter reduction through supply noise compensation

The non-linear nature of charge versus polarization in ferroelectric capacitors offers the unique opportunity to minimize jitter in phase locked loops (PLL). During the low effective capacitance state, the clock generation signal within the PLL has a high slew rate offering excellent timing characteristics. During the rest of the clock period, the high effective capacitance state is used to average inherent PLL noise. In this paper, we present the improved jitter that results when a PLL is implemented utilizing a strontium bismuth tantalate niobate based ferroelectric capacitor compared to conventional linear capacitor. In addition, we present the analysis of jitter in terms of capacitance characteristics of ferroelectric capacitor. When integrated on CMOS technology, PLLs based on ferroelectric capacitors have great potential for producing reduced jitter clock sources usable in future clock recovery and communication circuits.

"The clock generator is a critical component in high-speed wireline communication systems. The clocks in these systems mark time at precise regular intervals. Any deviation of the clock edges from these ideal time points is called jitter and it degrades the overall integrity of the communication system. This thesis looks at both phase locked loops (PLLs) and delay locked loops (DLLs) and their ability to provide these precise clocks. Expressions for the thermal noise-induced jitter in both the PLL and DLL are compared. From this, the DLL is shown to possess the potential for better jitter performance. However, to realise the potential of the DLL, another source of jitter peculiar to the DLL has to be reduced. This jitter in DLLs is caused by Static Phase Offset (SPO). The thesis details the causes of SPO and describes a number of good design practices for reducing it. It then describes an input and feedback clock phase interpolation technique which reduces SPO by half. Finally a novel chopping technique is used to essentially eliminate SPO resulting in a DLL which is ideal for high-speed wireline communication systems. Some of this work was published at the lEE Irish Signals and Systems Conference, which took place at Queens University Belfast, in June 2004."

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed technique can be applied to PLLs whose jitter is predominantly due to power supply noise. Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the supply voltage to the PLL and noting that PLL jitter is extremely sensitive to power supply variations, it is possible to introduce significant jitter into the PLL output which can be measured using a low-cost tester During production test, a regression model is used to predict the inherent PLL jitter from the measurement of power supply induced jitter.

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications. The new technique presented incorporates an accurate local reference frequency into the PLL structure. The key parameters of the new PLL structure are identified and the performance characterised. It is shown that the range of frequencies to which the new PLL structure can lock can be confined to a small region around the accurate local reference frequency. It is also shown that the new PLL structure provides other benefits such as a reduction of the VCO phase noise, allowing poor quality VCOs to be used in demanding applications. The new technique does not require any monitoring nor any switching of the local frequency reference signal which is always acting.

A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-μm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.

This paper presents a novel combination of two fully integrated phase-locked loops (PLLs) to control the oscillation frequency and modulation frequency of a switched injection-locked oscillator (SILO). The SILO is used as an active reflector transponder in a frequency-modulated continuous wave (FMCW) radar system. A fractional-N PLL (RF-PLL) with a tri-state phase-frequency detector (TSPFD) sets the oscillation frequency of the voltage controlled oscillator (VCO) to 2.45 GHz. Another integer-N PLL (modulation PLL) switches the tail current source of the VCO to achieve SILO behavior at the time when the RF-PLL is not controlling the VCO. The RF-PLL supports division ratios from 64 to 511 with a frequency resolution of 0.2 Hz. Reference spur levels are below -48 dBc while the out-of-band phase noise is -103 dBc/Hz at a 1MHz frequency offset. The modulation PLL is based on a Maneatis-cell ring-oscillator supporting modulation frequencies between 6MHz and 20 MHz. Furthermore, the duty cycle of the modulation signal can be set in steps of 0.8 %. Due to the novel TSPFD, the oscillation frequency of the SILO changes only by 36MHz within 10 minutes when the RF-PLL is inactive. The complete circuit is manufactured in a 180nm SiGe BiCMOS process and consumes a total power of 128mW.

The Costas loop can be considered an extension of the phase-locked loop (PLL). The PLL, invented 1932 by French engineer Henri de Belleszice, was first used for the synchronous reception of amplitude modulated radio signals with carrier (c). If the modulation index is less than 100%, the modulated signal is always in phase with the carrier signal (c), irrespective of the polarity of the modulating signal. The PLL then reconstructs a local carrier (loc) that is in phase the carrier (c) of the AM signal. The modulating signal is recovered by multiplying the AM signal with the local carrier (c) with subsequent lowpass filtering. This method of synchronous reception fails, however, when an AM signal with suppressed carrier is transmitted. Here the modulated signal is in phase with the (suppressed) carrier when the modulating signal is positive, but it is in antiphase with the carrier when the modulating signal is negative. When this AM signal is fed to the input of a PLL, it would create a local carrier (loc) that is in phase with the carrier when the modulating signal is positive, but in antiphase with the carrier when the modulating signal is negative. Recovery of the modulating signal is therefore not possible. The situation would be the same when the transmitted signal is a Binary Phase Shift Keying (BPSK) signal, a Quadrature Phase Shift Keying (QPSK) signal, or a Quadrature Amplitude Modulation (QAM) signal. This problem has been solved by the invention of the Costas loop by American engineer James P. Costas in 1956. The Costas loop is able to lock onto a modulated signal also in cases where the carrier is suppressed. When we compare the topology of a Costas loop with that of a PLL, we recognize that the PLL is built up from a cascade of three circuits: (1) a phase detector, (2) a loop filter, and (3) a voltage-controlled oscillator (VCO). There is a feedback path from the output of the VCO to the input of the phase detector. In case of the PLL, the input signal is propagated through this cascade of three blocks. There is only one signal path in the PLL. In contrast, there are two signal paths in the Costas loop: (1) a so-called “I branch” (in phase), (2) a so-called “Q branch” (quadrature phase). It is shown that with that configuration the loop is able to create a local carrier that is correctly locked to the carrier of the received signal even in cases when the carrier is suppressed. The invention of the Costas loop had a dramatic impact on any kind of communication receivers; one or more Costas loops are found in TV, radio, satellite communications, mobile phones, modems, etc.

This paper presents a high-speed, broadband phase -locked loop (PLL) for RF transceiver in 65nm CMOS process. Programmable structures are used to improve the lock speed of the PLL, the charge pump and loop filter can be adjusted by digital bit to reduce locked time of PLL. An integrated voltage-control oscillator (VCO) with 75% tuning range and a high-speed divider are used to accomplish all the frequencies. To achieve a wide tuning range while keep a low gain and a low phase noise, the VCO uses switched capacitor array. Finally, the PLL realizes 6-12 GHz wide frequency coverage. The phase noise performance at 6GHz is -113dBc/Hz@lMHz. The layout area is only 0.5265mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Working at 1. 2V supply voltage, the power consumption of the circuit is 11.3432 mW. The lock time of the PLL after using AFC is about 15. 258us.

CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5 V, 0.25 /spl mu/ CMOS PLL clock generator with a lock range of 100 MHz-400 MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.