Full CMOS video line-locked phase-locked loop system

An adaptive phase-locked loop (PLL) structure is proposed which offers fast and smooth tracking of phase-angle jumps. Correlatively, it offers soft startup stage and avoids undesired frequency swings caused by phase jumps. The adaptive mechanism adjusts the gain of frequency estimation loop in order to mitigate large transients of frequency during sudden phase angle variations. This reduces the coupling of phase and frequency variables and allows tremendously faster and smoother estimation of both variables. The proposed adaptive mechanism can be applied to different PLL and adaptive notch-filter systems three of which including the enhanced PLL (EPLL), the synchronous reference frame PLL (SRF-PLL), and the second order generalized integrator frequency-locked loop (SOGI-FLL) are studied in this paper.

Under distorted grid conditions with high bandwidth, synchronous reference frame (SRF) Phase Lock Loop (PLL) is able to work properly but increased bandwidth introduces harmonics which affect the PLL output and SRF PLL is also not able to produce accurate phase information under distorted grid conditions. This paper suggests a new phase detection technique based on cosine look-up table (cLUT) using sliding discrete Fourier transform (SDFT) for grid interfaced renewable energy sources (RES) under non-ideal grid conditions. The cLUT offers precise locking by acting as an integral controller such that the competence of the SDFT PLL is improved, steady state error in the output frequency of the voltage controlled oscillator (VCO) is reduced, and the input signals are also synchronized with generated sine and cosine reference signals. The proposed improved PLL system is mathematically analyzed and final enhancement to the system performance is studied under amplitude deviation and three phase voltage unbalance in the grid voltage and the results are compared with predictable SDFT PLL system.

The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the three phase utility interface inverters. The dynamic behavior of the closed loop PLL system is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system. In particular, the performance of the three phase PLL system is analyzed in the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by the nonlinear load conditions and measurement errors. The tracking errors under these distorted utility conditions are also derived. The phase tracking system is implemented in a digital manner using a digital signal processor (DSP) to verify the analytic results. The design considerations for the phase tracking system are deduced from the analytic and experimental results.

This paper describes to design and to examine the mechanical characteristics of high frequency jet ventilator. The device consists of Phase lock loop(PLL) system, solenoid valve driving control part and Air regulating system. This study is carried out by changing several factors such as endotracheal tube(E.T. tube)diameter, injector cannula diameter, 1%, and frequency(breaths/mim.) having direct effects on the gas exchange as well as parameters of the entrained gas by venturi effects, so as to measure the tidal volume and minute volume. This system characteristics were as follows : 1) Frequency : 6-594bpm 2) Inspiration time : 1-99% 3) Variance of input air pressure : 1-30PSI.

The asymmetric resonance response in electro-thermal piezoresistive cantilever resonators causes a need of an optimization treatment for taking parasitic actuation-sensing effects into account. An electronic reference circuit for signal subtraction, integrated with the cantilever resonator has the capability to reduce the effect of parasitic coupling. Measurement results demonstrated that a symmetric amplitude shape (Lorentzian) and an optimized phase characteristic (i.e., monotonically decreasing) were successfully extracted from an asymmetric resonance response. With the monotonic phase response, real-time frequency tracking can be easier to implement using a phase-locked loop (PLL) system. In this work, an electro-thermal piezoresistive cantilever resonator functionalized with self-assembled monolayers of chitosan-covered ZnO nanorod arrays as sensitive layers has been investigated under different relative humidity (rH) levels. Enhancement of resonance phase response has been demonstrated by implementing the reference signal subtraction. Subsequently, a lock-in amplifier integrated with PLL system (MFLI, Zurich Instruments, Zurich, Switzerland) was then employed for continuously tracking the resonant frequency. As a result, we find a good correlation of frequency shift (∆f0) with change in rH monitored using a commercial reference sensor.

CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5 V, 0.25 /spl mu/ CMOS PLL clock generator with a lock range of 100 MHz-400 MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

This paper studies two methods of addressing the DC component in phase-locked loop (PLL) systems. The DC component that may be actually present or may be generated by sensors, analog/digital converters or other signal conditioning systems, is a critical matter due to the fact that it causes low-frequency oscillations in the operation of PLL systems. Two methods are discussed in this paper where one of them adds a new loop inside the PLL to remove the DC and the other one uses a pre-filter to block the DC and then compensates for the filter's distortions at the output. The methods are compared from several points of view including: signal estimation, steady state performance, transient response, and computational complexity. The paper concludes that the first method offers a solution that is overall more desirable than the second one.

Phase-locked loop (PLL) is a key algorithm in a grid-connected power converter. The PLL must have excellent performance but consume minimum resources when implemented in a microcontroller.As the phase detector in the PLL system, causing the second harmonic signal, a notch filter is applied to cancel the second and higher harmonic that caused in PLL system to get better output signal. A simple second-order notch filter was implemented on the microcontroller.The performance of implemented digital PLL will be measured through several experiments. The experiment results show that the proposed digital PLL performs well after tested with emulatedvoltage sag, distorted input waveforms, and phase-jump conditions.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

On–off intermittency is observed in a mutually coupled phase-locked loop (PLL) system for both experiments and simulations. The system has two couplers between two PLLs for coupling and is designed to give good correspondence with dynamic systems with a periodic potential. In simulations, numerical calculations are performed on the governing equations of the PLL. In experiments, PLL IC modules and op-amps are used as PLL-cores and key components of couplers, respectively. The simulation results show coincidence with those of experiments. The properties of the burst signal in the observed intermittent signal are: the –1 power law of the amplitude distribution; and the –1.5 power law of the laminar duration time distribution. The power laws agree with the proper statistical features of the on–off intermittency.

The paper presents the description, analysis, and linearization in space-state form of three distinct phase-lock loop (PLL) systems, which are aimed for grid-following converters in a microgrid. PLL systems play an important role to assure proper phase angle and frequency tracking, which are fundamental to allow the proper operation of grid-connected converters and droop-operation of multiple converters in a microgrid. Due to its non-linear nature, accurate linearization methods must be used to include the dynamics of the PLL into stability analysis of an individual converter or of a cluster of grid-connected converters. The capability of analyzing dynamics by the means of reduced subsystems brings advantages of space-state form linearization when used for complex and non-linear systems such as the PLL. The accuracy of the described space-state linearized model is verified. Simulation results show that the error between the non-linear model and the space-state representation linearized model is below 2.5 %. The modelling presented is a good candidate to be used in analysis of local stability, when concerning an individual grid-following converter, as well for global stability, when concerning a cluster of converters within a microgrid.

A 29.5 to 31.7 GHz fully integrated phase locked loop (PLL) is presented in this paper. An integrated voltage-controlled oscillator (VCO) and a set of high-speed dividers are used to accomplish all the frequencies. The shunt peaking inductors is added in the first CML divider to higher the operating frequency and lower the power consumption. The current steering charge pump is utilized to improve switching time and thus allow high-speed operation. The PLL can be locked from 29.5 to 31.7 GHz. The PLL including buffers consumes 48mW from 1.2/0.7 V supplies. The output spectrum shows spur suppression higher than 23 dBc. Fabricated in a 65 nm CMOS process, the PLL occupies a chip area of 1.44 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .