Performance of Digital Phase Locked Loop Based on Notch Filter in Industrial ARM-Cortex Microcontrollers

Digital Phase Locked Loop (PLL) is an algorithm that is used to detect the phase, frequency, and amplitude of a signal. The output of digital PLL algorithm can be used as synchronization reference for grid connected inverter. A digital PLL algorithm is very popular to be used since its structure is very simple and it has high accuracy. However, the output of digital PLL is not stable if the input reference frequency is shifted from the pre-defined fundamental frequency and that condition will result an oscillation in digital PLL output. In this paper, an algorithm modification is employed using low pass filter and all pass filter to improve the digital PLL output response under various condition. All simulation results will be shown and compared to the conventional algorithm.

A CMOS PLL (phase-locked loop) system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is designed for use as a generic building block with large-scale CMOS video signal processing integrated circuits. The development of a custom test chip version of the PLL system is reported. A test chip version of the PLL system has been fabricated in 0.8 mu m CMOS technology and tested to verify functionality and examine acquisition and racking behavior. The test chip version of the PLL includes a bidirectional test bus monitor system used to observe 28 signals and input five signals for the purpose of assessing circuit operation details. The open-loop measured noise bandwidth of the RC VCO (voltage-controlled oscillator) is -30 dB at 350 Hz. The short term stability within one second is approximately +or-150 Hz or 20 p.p.m., corresponding to 1.3 ns jitter in one horizontal line period of 63.5 mu s. >

The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of the loop is also discussed, for both the noiseless and the noisy conditions.

The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang phase-locked loop is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.

An adaptive phase-locked loop (PLL) structure is proposed which offers fast and smooth tracking of phase-angle jumps. Correlatively, it offers soft startup stage and avoids undesired frequency swings caused by phase jumps. The adaptive mechanism adjusts the gain of frequency estimation loop in order to mitigate large transients of frequency during sudden phase angle variations. This reduces the coupling of phase and frequency variables and allows tremendously faster and smoother estimation of both variables. The proposed adaptive mechanism can be applied to different PLL and adaptive notch-filter systems three of which including the enhanced PLL (EPLL), the synchronous reference frame PLL (SRF-PLL), and the second order generalized integrator frequency-locked loop (SOGI-FLL) are studied in this paper.

The demand for highly energy-efficient circuits and systems has exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless transceivers and system clock generation for processors, memories, and I/O interfaces. Recent developments in fractional-N digital PLLs (DPLLs) [1]–[3] have shown great potential for achieving low-power operation and small chip area. However, none of these works have achieved power consumption below $500 \mu \mathrm {W}$ due to the number of building blocks operating at the oscillator frequency. Furthermore, the digitally controlled oscillators (DCOs) in [1]–[3] consume more than $250 \mu \mathrm {W}$ of power to achieve a good phase noise and a high-enough amplitude for DPLL locking. A digital sub-sampling architecture [1], [2], [4] can potentially reduce the overall power consumption by bypassing these high-frequency building blocks. Unfortunately, the absence of frequency acquisition makes such architecture vulnerable to sudden or large frequency disturbances. Even though a background frequency-locked loop (FLL) [1], [4] can be applied, it consumes large power due to the counter working at the DCO frequency. The typical solution to save power consumption is to turn off the FLL [2] after the PLL has been stabilized. Despite the benefit of the power reduction, a sub-sampling PLL has multiple frequency lock-in ranges near the integer multiple of the reference frequency, which could cause false locking if the frequency disturbances are within those ranges. To address the above issues, this work presents a fractional-N DPLL achieving a $265 \mu \mathrm {W}$ power consumption with robust phase and frequency acquisition with negligible power overhead in a 65nm CMOS technology. It also achieves an rms jitter of 2.8ps, which corresponds to an FoM of-236.8dB.

Phase locked loops (PLLs) are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid Electromagnetic Interference (EMI). Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow (Fig. 1 (a)). That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) is needed to obtain smaller output frequency steps than reference frequency. It is important to make Frac-N PLLs as soon as possible to meet a market opportunity. However, it takes long time to make them from scratch. One of answers would be Frac-N digital PLL whose most part is digital circuit which is quickly designed with RTL. However, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [1], [2]. The TDC is a key analog block that requires long time to design and calibration which increases complexity. If we have a fractional divider (FDIV) to make a Frac-N PLL by just connecting to an Int-N PLL, it is useful. Some Frac-N PLLs [3], [4] have been published and they have FDIVs. In [3], extra coarse frequency control is needed to generate the frequency information, increasing complexity. In [4], two-step phase interpolation has been proposed to reduce $\Delta \sum$ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector. It is tough to apply this structure to ordinary PLLs.

Under distorted grid conditions with high bandwidth, synchronous reference frame (SRF) Phase Lock Loop (PLL) is able to work properly but increased bandwidth introduces harmonics which affect the PLL output and SRF PLL is also not able to produce accurate phase information under distorted grid conditions. This paper suggests a new phase detection technique based on cosine look-up table (cLUT) using sliding discrete Fourier transform (SDFT) for grid interfaced renewable energy sources (RES) under non-ideal grid conditions. The cLUT offers precise locking by acting as an integral controller such that the competence of the SDFT PLL is improved, steady state error in the output frequency of the voltage controlled oscillator (VCO) is reduced, and the input signals are also synchronized with generated sine and cosine reference signals. The proposed improved PLL system is mathematically analyzed and final enhancement to the system performance is studied under amplitude deviation and three phase voltage unbalance in the grid voltage and the results are compared with predictable SDFT PLL system.

In grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widely used grid synchronization technique, owing to its simple implementation. However, in power grids some very common problems, such as voltage distortion, voltage unbalance, and frequency instability make synchronization a challenging task. The performance of the conventional synchronous reference frame PLL (SRF-PLL) is greatly reduced in the presence of distorted grid conditions. For a polluted grid some advance PLL techniques have been proposed, such as moving average filter PLL (MAF-PLL) and cascaded delayed signal cancellation PLL (CDSC-PLL). These techniques have been mostly evaluated in the presence of odd and even harmonics but the effects of interharmonics on these synchronization techniques still needs to be investigated. In this paper, a detailed performance comparison has been made between SRF-PLL, MAF-PLL, and CDSC-PLL for grid voltages contaminated with interharmonics in the presence of different grid disturbances, such as frequency jump, phase angle jump, and dc offset. The techniques are simulated using Matlab/Simulink. The CDSC-PLL shows excellent performance as compared with other techniques in terms of dynamic response as it settles to frequency step change in a half cycle but the presence of interharmonics greatly reduces its filtering capability. On the other hand, MAF-PLL gives a ripple free behavior in frequency estimation but with a much slower dynamic response as it settles to a frequency step change in more than three cycles. SRF-PLL only performs well under harmonics free grid voltages.

The traditional phase locked loop (PLL) is realized by analog circuit. Compared with PLL realized by traditional analog circuit, digital phase locked loop (DPLL) has the advantages of high precision, not affected by temperature and voltage, adjustable loop bandwidth and center frequency, and easy to construct high-order PLL. With the rapid development of communication technology and integrated circuit technology, DPLL will be more widely used. In this paper, the PLL macroblock is used to design and realize the functions of frequency division, frequency doubling and phase locking in Quartus II development environment. The validity of the design and application of the DPLL is verified by practical verification.

Phase-locked loops (PLL) are essential building blocks in wireless transceivers. Concerning data transmission and reception the performance of the PLL is crucial for the overall performance of the whole system. The transmitter architecture of the presented system does not use mixers but the PLL itself for FSK modulation. Therefore especially the bandwidth of the PLL influences performance parameters. As the PLL bandwidth is subject to significant variations due to process, temperature and supply voltage, bandwidth calibration is an important measure to ensure the PLL performance specifications. This paper presents two methods which use building blocks of an existing transceiver to calibrate the PLL bandwidth. Both methods use existing features of the transceiver architecture and therefore require only minimal adjustments and in principal no additional building blocks in order to accomplish bandwidth calibration. The first method uses an ADC to measure the PLL Loop Filter Voltage and the second employs the receiver to observe the frequency and phase of the PLL output signal. The proposed methods have been verified by measurements using a test chip implemented in a low-cost Infineon 130 nm CMOS process and an FPGA board. The variation of the PLL bandwidth after calibration is lower than ±10% compared to more than ±60% for an uncalibrated PLL. The time needed for calibration lies between 32 μs and 200 μs.

This paper describes to design and to examine the mechanical characteristics of high frequency jet ventilator. The device consists of Phase lock loop(PLL) system, solenoid valve driving control part and Air regulating system. This study is carried out by changing several factors such as endotracheal tube(E.T. tube)diameter, injector cannula diameter, 1%, and frequency(breaths/mim.) having direct effects on the gas exchange as well as parameters of the entrained gas by venturi effects, so as to measure the tidal volume and minute volume. This system characteristics were as follows : 1) Frequency : 6-594bpm 2) Inspiration time : 1-99% 3) Variance of input air pressure : 1-30PSI.

The analysis and design of the phase-locked loop (PLL) system is presented for the phase tracking system of the three phase utility interface inverters. The dynamic behavior of the closed loop PLL system is investigated in both continuous and discrete-time domains, and the optimization method is considered for the second order PLL system. In particular, the performance of the three phase PLL system is analyzed in the distorted utility conditions such as the phase unbalancing, harmonics, and offset caused by the nonlinear load conditions and measurement errors. The tracking errors under these distorted utility conditions are also derived. The phase tracking system is implemented in a digital manner using a digital signal processor (DSP) to verify the analytic results. The design considerations for the phase tracking system are deduced from the analytic and experimental results.

The conventional PLL (phase locked loop) frequency synthesizer has a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are a serious problem because the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit which makes the negligible overshoot and much shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. Also, the hardware complexity and power consumption are decreased to about 28%, as compared with the conventional DH-PLL. The high speed switching characteristic in the frequency synthesis process is verified by computer simulation.

Phase locked loop (PLL) system implementation in information subsystem of active voltage rectifier (AVR) is determined by requirement of power factor correction and suppression of the higher harmonics in current reference signal in nonideal mains voltage conditions. The method of phase locked loop system synthesis based on state space formalism is proposed. Control algorithm is based on state feedback control principals which means using a feedback signal composed from the components of the object's state as the controlled input. State regulator for PLL control system is synthesized. For immeasurable object's states estimation reduced-order observer is used. Digital PLL system synthesis is provided. Transition from differential equations of state to the difference equations of state is carried out to describe processes in the digital control system. The model of three-phase active voltage rectifier with synthesized phase locked loop is made. Modelling results shows the capability of AVR control system with synthesized PLL to carry out compensation of reactive power and to correct current shape in the mains.