Short locking time and low jitter phase-locked loop based on slope charge pump control

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 mum technology, the PFD and the CP dissipate 3.73 mW and a 460 muW DC power from a IV supply, respectively. The occupied chip area of the PFD is 68times24 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and that of the CP is 68times23 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a spurious free dynamic range of a 80 dBc, a phase noise of a -95 dBc/Hz at 100 kHz offset, a low power and a small layout area the presented PFD and CP are suitable for integrated radio applications operating between 2.4 GHz and 10 GHz, such as 802.11 and WiMax for example.

Design of a stable Phase Locked Loop (PLL) working in MHz frequency range is proposed. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. All the blocks of PLL i.e Phase Frequency Detector (PFD), Charge Pump and Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) are carefully designed and integrated. PFD is implemented using D flip-flop and is made to detect minimal phase errors. CPLF has differential design for noise immunity and for avoiding floating conditions. The 15 stage VCO gives frequency range of 30 MHz to 200 MHz for input voltage range of 0.5 V to 1.05 V with a resistor for optimizing linearity. The integrated PLL is stable in the output frequency range of 44 MHz to 200 MHz for given input frequency range of 11 MHz to 50 MHz. The designs are implemented in 180 nm technology and for a supply voltage of 1.8 V.

The design and analysis of the Phase Locked Loop (PLL) is suggested in this proposed paper. A feedback control system called a “Phase Locked Loop (PLL)” block automatically modifies a locally generated signals phase to match an input signals phase. PLL works by creating an oscillator frequency that matches the input signal frequency. The Phase Frequency Detector (PFD) in PLL is designed with 4 transistors anda charge pump (CP) is also designed with a reduction of only 4 transistors. To reduce the ripple, a loop filter is used, and a Current Starved five-stage voltage controller oscillator (CS-VCO)circuit with 22 transistors is used. Here Frequency Divider (FD) is designed with 9 transistors. The simulation is carried out in the GPDK90Nm technology. In this paper, the PLL and its block simulation results are provided. It is shown that a 1V D.C. supply delivers 22.63uW of power in a proposed PLL.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

This paper presents the modeling and design activity of a PLL (Phase-Locked Loop) architecture to generate the clock reference for the new ESA Spacefibre standard for on-board satellite communications up to 6.25 Gbps. Starting from a 6.25 GHz VCO rad-hard design, integrated in 65 nm technology within an IMEC-University of Pisa collaboration, this work presents a PLL architecture including configurable integer divider, down to a reference signal of 156.25 MHz, phase-frequency detector, charge pump and passive loop filter. Modeling and simulation analysis, carried out in Keysight ADS environment, show that a fully integrated solution can be achieved with a 6 MHz low-pass PLL loop filter whose passive devices can be integrated on chip with an area of about 4600 µm2. The PLL phase noise performance are in line with that of the original VCO, and for the stability a gain and phase margins of 86 dB and 50° are achieved. PLL lock time is about 555 ns. A preliminary circuit for the charge pump implementation is also proposed.

The major effects defining reference spurs level of the integer-N phase-locked loop (PLL) frequency synthesizer are described. The behavioral model of the PLL for evaluating reference spurs level has been developed in CAD Keysight ADS. The model takes into account time delay between output signals of the phase-frequency detector (PFD) and delay in the PFD reset path; charge pump current mismatch; charge pump current leakage; charge pump switching time mismatch. The design issues of SOI CMOS PLL functional blocks (FB) based on the proposed behavioral model, have been provided.

Comprehensive analysis of linear phase frequency detectors in phase-locked loops

A low power low phase noise wide frequency range PLL

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

Phase lock loop (PLL) operates at higher frequency and due to the increased switching, the power consumed is high. The increase in demand of applications in communications systems has led to fully integrated, minimal power and high performance PLL. There is a demand for low power applications and hence various methods have been emerging. The power of the PLL has to be reduced and optimized by reducing the power of all the sub-blocks of PLL. Adaptive voltage level (AVLS) technique is incorporated in the circuit to reduce power consumption. The phase detector of the PLL is replaced with a phase frequency detector with dead zone which is used to reduce the power of the PLL. The number of transistors is also reduced thereby reducing the area of the PLL. Also MOSFETs are used for the design of loop filter. The circuits are realized using CMOS 180nm technology in Cadence Virtuoso and simulated using Cadence Spectre. Proposed modified PLL architecture's is compared w.r.t. reference PLL architectures at various frequencies. Proposed PLL architectures consumes very less power compared to reference PLL architectures even at higher frequency (>1 GHz).

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

A low jitter, low spur multiphase phase-locked loop (PLL) for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output. In this design, a noise and matching improved voltage-controlled oscillator (VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks. By good matching achieved in the charge pump and careful choice of the loop filter bandwidth, the reference spur is suppressed. A phase noise of −118.42 dBc/Hz at a frequency offset of 1 MHz, RMS jitter of 1.53 ps and reference spur of −66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement. The chip was manufactured in 0.13 μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm2 area.

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 mum technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.