PFD with Dead zone based Low Power Modified Phase Lock Loop using AVLS Technique

This paper presents the modeling and design activity of a PLL (Phase-Locked Loop) architecture to generate the clock reference for the new ESA Spacefibre standard for on-board satellite communications up to 6.25 Gbps. Starting from a 6.25 GHz VCO rad-hard design, integrated in 65 nm technology within an IMEC-University of Pisa collaboration, this work presents a PLL architecture including configurable integer divider, down to a reference signal of 156.25 MHz, phase-frequency detector, charge pump and passive loop filter. Modeling and simulation analysis, carried out in Keysight ADS environment, show that a fully integrated solution can be achieved with a 6 MHz low-pass PLL loop filter whose passive devices can be integrated on chip with an area of about 4600 µm2. The PLL phase noise performance are in line with that of the original VCO, and for the stability a gain and phase margins of 86 dB and 50° are achieved. PLL lock time is about 555 ns. A preliminary circuit for the charge pump implementation is also proposed.

Comprehensive analysis of linear phase frequency detectors in phase-locked loops

This paper presents the circuit level implementation and analysis of the Phase Locked Loop (PLL) architecture for clock generation in Analog to Digital Converters (ADCs). The PLLs are required to generate low-noise or low-jitter clock signals and at the same time need to achieve fast locking. The Analog to Digital Converters require a clock generator whose clock output should have jitter less than 1 ps to have higher Effective Number Of Bits (ENOB). Catering the needs of the ADC, low-jitter PLL architecture is proposed which consist of pre-charged phase-frequency detector, charge pump, second order loop filter and a current-starved inverter based Voltage Controlled Oscillator (VCO) circuit. The integrated PLL architecture is implemented and simulated using CADENCE Analog Design Environment. It is synthesized using TSMC 0.18µm, six-metal technology. The lock range (operating frequency range) of the PLL is 95MHz to 145 MHz with a center frequency of 100 MHz and a jitter of around 700 fs are obtained as a result of its verification at all process corners.

Electric vehicles (EVs) are a promising solution to reduce carbon dioxide (CO2) emissions, but this reduction depends on the fraction of renewable sources used to generate electricity. Wind energy is thus a vital candidate and has experienced a remarkable surge recently, establishing itself as a leading renewable power source worldwide. The research on Direct-Driven Permanent Magnet Synchronous Generator (PMSG)-based type 4 wind farms has indicated that the Phase-locked Loop (PLL) bandwidth significantly impacts Sub-Synchronous Resonance (SSR). However, the influence of PLL architecture on SSR remains unexplored and warrants investigation. Therefore, this paper investigates PLL architectural variations in PLL Loop Filter (LF) to understand their impact on SSR in type 4 wind farms. Specifically, an in-depth analysis of the Notch Filter (NF)-based enhanced PLL is conducted using eigenvalue analysis of the admittance model of a PMSG-based type 4 wind farm. The findings demonstrate that the NF-based enhanced PLL exhibits superior performance and improved passivity in the sub-synchronous frequency range, limiting the risk of SSR below 20 Hz. Additionally, Nyquist plots are employed to assess the impact on system stability resulting in increased stability margins. In the future, it is recommended to further investigate and optimize the PLL to mitigate SSR in wind farms.

The deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, which increases the phase noise in the output spectrum of the PLL. Therefore, in this work a new variable-delay element (VDE) is incorporated in the PFD to reduce the dead zone and consequently the phase noise of the PLL. The performance of the proposed PFD incorporated in PLL is analyzed using cadence virtuoso 90 nm CMOS technology, achieving a phase noise of −148.89 dBc/Hz at a frequency offset of 1 MHz, a lock time of 6.01 us, a power of 0.056 mW, and a dead zone of 110.5 ps, while operating at 3.5 GHz of frequency, making it suitable for 5G applications.

Introduction Frequency synthesizers are pervasively utilized in almost every electronic system for generation of the well-defined clock frequencies of interest. For instance, in the modern wireless transceiver, a phase-locked loop (PLL) is commonly used to generate RF frequencies to up-convert and down-convert the analog signal. On the baseband side, the mixed-signal circuit, such as switched-capacitor filters, as well as digital VLSI also require PLLs to synthesize various clock domains. Moreover, the trend of future electronic design will continue to integrate more functionality, support multiple standards, and multi-channels in a system-on-chip (SoC) platform, which will inevitably increase the number of frequency synthesizers for various analog and digital circuit blocks. As a result, minimizing the power and area consumption of a frequency synthesizer becomes increasingly critical, or it can become the dominant cost factor in the overall system. This system trend has been driving PLL design towards more reconfigurability, wider tuning range and lower cost. The digitally-assisted PLL design concept becomes a natural consequence of this trend, as the flexibility offered via digital means is always appealing. Conventionally, the frequency synthesizer is implemented using an analog approach, i.e., the charge-pump PLL, as shown in Figure 4.1(a). The basic operation of this type of PLL has been well documented in textbooks and the literature [1, 2]. In brief, it processes the phase information in the analog domain via a phase frequency detector and a charge-pump circuit, so that the phase difference turns into current pulses. This current signal is then converted into voltage form via the analog loop filter, which typically consists of capacitor and resistor array. Some degree of digitally-assisted concept was adopted for this type of PLL, mainly to digitally reconfigure the analog loop filter and voltage-controlled oscillator (VCO). For example, the PLL may be required to support different PLL loop bandwidths and/or a wide VCO tuning range. The digitally switched capacitor or resistor bank is a common choice to support this kind of operation. While this analog PLL topology has been widely adopted and proven in both the literature and commercial products, it presents a challenge to scale with technology. The analog loop filter is typically composed of bulky passive components whose values are determined by the desirable PLL loop bandwidth, and cannot be arbitrarily reduced.

The design and analysis of the Phase Locked Loop (PLL) is suggested in this proposed paper. A feedback control system called a “Phase Locked Loop (PLL)” block automatically modifies a locally generated signals phase to match an input signals phase. PLL works by creating an oscillator frequency that matches the input signal frequency. The Phase Frequency Detector (PFD) in PLL is designed with 4 transistors anda charge pump (CP) is also designed with a reduction of only 4 transistors. To reduce the ripple, a loop filter is used, and a Current Starved five-stage voltage controller oscillator (CS-VCO)circuit with 22 transistors is used. Here Frequency Divider (FD) is designed with 9 transistors. The simulation is carried out in the GPDK90Nm technology. In this paper, the PLL and its block simulation results are provided. It is shown that a 1V D.C. supply delivers 22.63uW of power in a proposed PLL.

This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.

Design of a stable Phase Locked Loop (PLL) working in MHz frequency range is proposed. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. All the blocks of PLL i.e Phase Frequency Detector (PFD), Charge Pump and Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) are carefully designed and integrated. PFD is implemented using D flip-flop and is made to detect minimal phase errors. CPLF has differential design for noise immunity and for avoiding floating conditions. The 15 stage VCO gives frequency range of 30 MHz to 200 MHz for input voltage range of 0.5 V to 1.05 V with a resistor for optimizing linearity. The integrated PLL is stable in the output frequency range of 44 MHz to 200 MHz for given input frequency range of 11 MHz to 50 MHz. The designs are implemented in 180 nm technology and for a supply voltage of 1.8 V.

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 mum technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

The major effects defining reference spurs level of the integer-N phase-locked loop (PLL) frequency synthesizer are described. The behavioral model of the PLL for evaluating reference spurs level has been developed in CAD Keysight ADS. The model takes into account time delay between output signals of the phase-frequency detector (PFD) and delay in the PFD reset path; charge pump current mismatch; charge pump current leakage; charge pump switching time mismatch. The design issues of SOI CMOS PLL functional blocks (FB) based on the proposed behavioral model, have been provided.

An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 mum technology, the PFD and the CP dissipate 3.73 mW and a 460 muW DC power from a IV supply, respectively. The occupied chip area of the PFD is 68times24 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and that of the CP is 68times23 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a spurious free dynamic range of a 80 dBc, a phase noise of a -95 dBc/Hz at 100 kHz offset, a low power and a small layout area the presented PFD and CP are suitable for integrated radio applications operating between 2.4 GHz and 10 GHz, such as 802.11 and WiMax for example.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.