Challenges and emerging trends of DSP-enabled frequency synthesizers

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 mum technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

A low power low phase noise wide frequency range PLL

The major effects defining reference spurs level of the integer-N phase-locked loop (PLL) frequency synthesizer are described. The behavioral model of the PLL for evaluating reference spurs level has been developed in CAD Keysight ADS. The model takes into account time delay between output signals of the phase-frequency detector (PFD) and delay in the PFD reset path; charge pump current mismatch; charge pump current leakage; charge pump switching time mismatch. The design issues of SOI CMOS PLL functional blocks (FB) based on the proposed behavioral model, have been provided.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Comprehensive analysis of linear phase frequency detectors in phase-locked loops

This paper introduces a new-type phase-frequency-detector (PFD) for charge pump phase-locked-loops (CPPLLs). As the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property. The experimental results of the proposed PFD show the reduced frequency acquisition time by about 30% compared with the conventional PFD in the case of 70MHz voltage-controlled-oscillator (VCO) frequency hopping for PCS mobile applications. The PFD is designed and simulated by SPECTRE and the prototype, together with a frequency synthesizer, has been fabricated in a 0.5/spl mu/m BiCMOS technology.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A second-order passive lead-lag loop filter for analog phase-locked loop (PLLs) is modified in this paper for the third-order charge-pump PLLs (CPPLLs). The analysis shows that the CPPLL employing the modified loop filter results in smaller area, lower power consumption, or better noise performance than the CPPLL employing the conventional loop filter.

Phase lock loop (PLL) operates at higher frequency and due to the increased switching, the power consumed is high. The increase in demand of applications in communications systems has led to fully integrated, minimal power and high performance PLL. There is a demand for low power applications and hence various methods have been emerging. The power of the PLL has to be reduced and optimized by reducing the power of all the sub-blocks of PLL. Adaptive voltage level (AVLS) technique is incorporated in the circuit to reduce power consumption. The phase detector of the PLL is replaced with a phase frequency detector with dead zone which is used to reduce the power of the PLL. The number of transistors is also reduced thereby reducing the area of the PLL. Also MOSFETs are used for the design of loop filter. The circuits are realized using CMOS 180nm technology in Cadence Virtuoso and simulated using Cadence Spectre. Proposed modified PLL architecture's is compared w.r.t. reference PLL architectures at various frequencies. Proposed PLL architectures consumes very less power compared to reference PLL architectures even at higher frequency (>1 GHz).

The design and analysis of the Phase Locked Loop (PLL) is suggested in this proposed paper. A feedback control system called a “Phase Locked Loop (PLL)” block automatically modifies a locally generated signals phase to match an input signals phase. PLL works by creating an oscillator frequency that matches the input signal frequency. The Phase Frequency Detector (PFD) in PLL is designed with 4 transistors anda charge pump (CP) is also designed with a reduction of only 4 transistors. To reduce the ripple, a loop filter is used, and a Current Starved five-stage voltage controller oscillator (CS-VCO)circuit with 22 transistors is used. Here Frequency Divider (FD) is designed with 9 transistors. The simulation is carried out in the GPDK90Nm technology. In this paper, the PLL and its block simulation results are provided. It is shown that a 1V D.C. supply delivers 22.63uW of power in a proposed PLL.

The phase locked loop (PLL) is a control system that compares the phase of the output signal with that of the input signal and proportionally varies its output based on the phase difference between them. PLL most prolifically finds its applications in frequency generation, clock and data recovery, carrier frequency generation in modulation and demodulation, frequency synthesizers, jitter and skew reduction, and many more. Mixed-signal and digital circuits employ PLL for clock generation to get the synchronous transactions with the clock. So it is mandatory to properly design the PLL to obtain minimum jitter on the clock edges. The PLL designed in this work was based on the famous charge-pump (CP) architecture and was implemented using the semiconductor laboratory (SCL) 180 nm technology in Cadence Virtuoso. This work uses NOR-based PFD using TSPC latches, Transmission gate CP, Current Starved VCO, and TSPC-based divider circuit. The proposed model of PLL has phase noise of the PLL as −113 dBc/Hz, the power consumption of the total PLL as 3.2 mW at 1.8 V power supply with deterministic jitter of about 5.62 ps and the settling time of the control voltage as 850 ns.

Design of a stable Phase Locked Loop (PLL) working in MHz frequency range is proposed. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. All the blocks of PLL i.e Phase Frequency Detector (PFD), Charge Pump and Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) are carefully designed and integrated. PFD is implemented using D flip-flop and is made to detect minimal phase errors. CPLF has differential design for noise immunity and for avoiding floating conditions. The 15 stage VCO gives frequency range of 30 MHz to 200 MHz for input voltage range of 0.5 V to 1.05 V with a resistor for optimizing linearity. The integrated PLL is stable in the output frequency range of 44 MHz to 200 MHz for given input frequency range of 11 MHz to 50 MHz. The designs are implemented in 180 nm technology and for a supply voltage of 1.8 V.