A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits

Synthesis tools for approximate sequential circuits require the ability to quickly, efficiently, and automatically characterize and bound the errors produced by the circuits. Previous approaches to characterize errors in approximate sequential circuits have been based on simulations spanning all cycles of a sequential computation. These approaches, however, are not scalable and only accommodate small circuit modules and short computation times. In this paper, we observe that the statistical properties of errors in many approximate sequential circuits follow patterns that can be easily learned. Therefore, statistical error characteristics of these approximate sequential circuits can be predicted with high accuracy using only a few cycles of characterization data. Based on this novel observation, we propose a methodology for predicting error statistics in approximate sequential circuits that is accurate, fully automated, and has significantly lower overhead than prior approaches. Our methodology is robust to changes in predicted error metrics, circuit input distributions, and types of approximate hardware modules used in approximate circuits. We demonstrate the accuracy and scalability of our approach over a range of sequential circuits. On average, prediction inaccuracy is less than 2% and error characterization time is reduced by 99% compared to a simulation-based approach.

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.

The multiply-accumulate unit (MAC) is common in applications like as image and digital signal processing. In order to increase the speed and reduce the power consumption, approximate compressors can be used in the stages of computations. In this paper, three 5:2 approximate compressors are proposed and used in 8-bit MAC implementation. Proposed approximate MAC circuits were synthesized using Synopsys Design Compiler and compared with previous designs that used approximate circuits. Examining the error evaluation parameters including ER , MED and NMED shows that the proposed MUX_C3 design is 6%, 58.8% and 58.7% better than other existing designs, respectively. In performance-error rate compromising (PDP- NMED ), it has been shown that the proposed designs have the least error. To evaluate the quality of the results in image processing applications, the proposed approximate MAC were used in the image multiplication operation in MATLAB software. Measurement of SSIM and PSNR parameters show acceptable results.

Approximate computing finds its application in image processing, machine learning, data mining and multimedia data processing. The paper proposes a scalable and lightweight <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> approximate multiplier, which is designed to efficiently utilize the FPGA resources. We have divided the partial product matrix and selectively chosen the input variables for the effective usage of the LUTs and carry-chain. The bit error position due to the approximation is reduced by assigning the possible lower bits to ‘1’ which reduces the maximum error magnitude from 16 to 4. The proposed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> approximate multiplier achieves a reduction in area, power and latency of 26.7%, 57.6% and 60.1% respectively compared to the Xilinx multiplier IP. The proposed multiplier is used as a building block to implement <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> approximate multipliers for image sharpening applications. We achieve a high PSNR value of 69.4 dB using the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> approximate multiplier.

The field of approximate computing has garnered significant interest as a promising area for relatively error-resistant applications. At its core, approximate computing revolves around a trade-off between efficiency and accuracy. To optimize power consumption, delay, and area, a certain level of accuracy is sacrificed, provided it remains within acceptable limits. This research introduces a novel design for an approximate 4:2 compressor. Two distinct configurations for implementing this compressor are proposed and evaluated within the framework of an 8x8 Dadda multiplier. The study assesses both technology-dependent and technology-independent parameters, comparing them with the most recent approximate multipliers reported in recent literature. The performance of these multipliers is tested using a 45-nm standard CMOS technology node. Additionally, the quality and precision of the proposed approximate multiplier are evaluated using a range of statistical metrics. To demonstrate their practical utility, the proposed multipliers are applied to image processing tasks. The results indicate that the proposed designs outperform existing approximate multipliers in terms of efficiency for image processing applications.

Introduction: Approximate computing is one of the techniques used to balance trade-offs between power, speed, and area in a resource-limited environment. Mainly, a large amount of power consumption and significant delay are caused by the arithmetic operations, in which the multiplication process generates more power consumption and high latency. In order to save energy and increase speed, an approximate multiplier is a good candidate for use in error-resilient applications like signal and image processing. This study proposes a truncated adaptive approximate radix-8 Booth multiplier (TAARBM). It aims to apply partial product truncation to construct an approximation multiplier design for error-tolerant applications, such as image processing. Methods: The truncation strategy is adopted to minimize the partial product array (PPA) of the radix- 8 Booth multiplier, as an additional PPA creates complexity in the operations. Moreover, the Booth encoder in the radix-8 Booth multiplier is enhanced with an Approximate Booth Encoder (ABE), which replaces adders with simple shift-logic operations to speed up the operation. The path Selectable and Reconfigurable Hybrid Adder (pSRHA) is introduced in the TAARBM architecture to minimize the delay. The design is coded in Verilog-HDL, simulated on the Xilinx Vivado simulator, and implemented on an FPGA board. Results: The simulation results demonstrate that the proposed 16-bit TAARBM consumes 4.110 W power and 1.805 ns delay. The proposed design accomplishes error metrics of 402.96 MED, 0.00975 MRED, 1300 AED, and 0.0120 ARE. Discussion: The simulation results show the proposed design';s high-speed operation. Moreover, the proposed approximate multiplier is designed with a low error rate, as shown by performing different error metrics like MED, MRED, AED, and ARE. In addition, the FIR filter is designed with the proposed TAARBM to perform the image denoising process on five benchmark images. For this application, the image quality measures, such as PSNR and SSIM, are calculated, which are higher for the proposed design. Conclusion: The comparison of the obtained results with existing references proves the present validity of the current work. Various error metrics and synthesis results validate the effectiveness of the proposed approximate multiplier. Moreover, the proposed multiplier is used in an image processing application for the denoising process.

Adders and multipliers form the significant components in all kind of digital applications and has always been a thought-provoking topic for the researchers. Multiplication process will initially find out the set of partial products and then groups the partial products according to their respective bit positions and takes the summation. Among the phases of multiplication, partial product reduction tree consumes the maximum power and area as it is done using several adders. In this paper, a High Speed, Low Power Approximate Multiplier is proposed in which a new 4–2 compressor is being projected and is made use while performing vector merge addition after transforming the partial product terms to lead varying probability terms. Simulation results shows that the proposed Approximate Multiplier achieved 3.19% less Area, 53.74% less Delay, 3.79% less Power compared to Approximate Multiplier [6] and 31% less Area, 81.35% less Delay and 59.83% less Power compared to that of an Exact Multiplier. When we make use of Approximate Multipliers, there are likelihoods of error occurring in some cases. Hence approximate multipliers are suggested only for Error Resilient applications. Video compression, Digital Image processing and Test Data compression can be categorized as such applications. The proposed approximate multiplier takes less Power, Area and Time and also can be paralleled to the existing approximate multiplier algorithms. Hence for Error resilient application, it is always sagacious to use less power consuming constituents since power is a crucial one to save in the current scenario.

Approximate computing represents a computational paradigm that trades off a slight reduction in accuracy for significant performance improvements. One of the fundamental operations that can leverage approximate techniques is multiplication, which is used substantially in applications like image/video processing and machine learning. This work proposes an approximate 8-bit multiplier design for FPGA-based circuits. This multiplier, by exploiting the FPGA primitives, demonstrates excellent performance regarding error metrics, critical path delay, and power dissipation with minimal LUT utilization. More precisely, the proposed design reduces LUT usage by 43% and PDP by 59% compared to the exact multiplier while incurring a mean error distance of only 102.57. The proposed approximate multiplier is used in two image processing applications to assess the actual advantages in real-world applications. The proposed design achieves a reasonable PSNR in the image processing flow, demonstrating high-quality results with a low error rate.

Approximate computing as a promising technique is widely used in a variety of error tolerance applications, such as computer vision, machine learning and image processing. Since multiplication is one of the basic arithmetic operations used extensively among these applications which creates a great potential to reduce the circuit’s area and power consumption by exploring approximate multipliers. In this paper, we present FHAM, a novel methodology for FPGA-based approximate softcore multiplier architecture via modifying INIT parameter values in LUT primitives. Our proposed approximate multipliers can achieve up to 24.4%, 52.9%, 56.4% improvement in delay, area and power over Xilinx soft multiplier IP core, respectively. We deployed the proposed approximate multiplier designs in the application of image blending, the results demonstrate that proposed multiplier design has a better accuracy-hardware tradeoff than other designs.

Adders play a critical role as primary modules in circuit design, supporting error-tolerant applications such as machine learning, digital image processing, and signal processing. Therefore, the development of adders with low power consumption and energy efficiency is of utmost importance. Approximate adders outperform exact adders in VLSI chips. Among approximate adders, the hybridization of Single Exact and Single Approximation (SESA) and Single Exact and Dual Approximation (SEDA) techniques has emerged as a promising solution. These hybrid adders offer superior power and energy savings relative to other accurate and approximate adder designs. In this scheme, we propose the integration of hybrid radix-4 adders with approximation adders to achieve enhanced performance and pave the way for future hybrid approximate adder circuits. Extensive simulations validated the efficacy of the proposed approach. Furthermore, practical applications demonstrated the versatility and potential of hybrid adders in real-world scenarios. The proposed methodology ensures cost-effectiveness and facilitates seamless future updates and extensions. Overall, this research contributes to the advancement of efficient and low-power adder designs, addressing the evolving requirements of modern digital systems.

We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the worst-case relative error, abbreviated as WCRE. WCRE represents an important error metric relevant in many applications including, e.g., approximation of neural network HW architectures. The method integrates SAT-based error evaluation of approximate circuits into a verifiability-driven search algorithm based on Cartesian genetic programming. We implement the method in our framework ADAC that provides various techniques for automated design of arithmetic circuits. Our experimental evaluation shows that, in many cases, the method offers a superior scalability and allows us to construct, within a few hours, high-quality approximations (providing trade-offs between the WCRE and size) for circuits with up to 32-bit operands. As such, it significantly improves the capabilities of ADAC.

Approximate computing has been recognized as an effective low power technique for applications with intrinsic error tolerance, such as image processing and machine learning. Existing efforts on this front are mostly focused on approximate circuit design, approximate logic synthesis or processor architecture approximation techniques. This work aims at how to make good use of approximate circuits at system and block level. In particular, approximation aware scheduling, functional unit allocation and binding algorithms are developed for data intensive applications. Simple yet credible error models, which are essential for precision control in the optimizations, are investigated. The algorithms are further extended to include bitwidth optimization in fixed point computations. Experimental results, including those from Verilog simulations, indicate that the proposed techniques facilitate desired energy savings under latency and accuracy constraints.

OHC-Sim is a simulation package for design of an oil-hydraulic circuit and analysis of its dynamic characteristics. To make the design and the improvement processes of an oil-hydraulic circuit more effective and systematic, OHC-Sim had been developed with the support of JFPS and has been enhanced in the research committee in JFPS. OHC-Sim is executable on personal computers in Windows® environment, and provides easy design and improvement of an oil-hydraulic circuit based on the simulated results. However, in order to enhance the use of OHC-Sim, it is desirable that the simulation of the dynamic characteristics of a pneumatic circuit becomes executable on OHC-Sim. In this study, to enhance OHC-Sim to the simulation of a pneumatic circuit, the bond-graph models for pneumatic components are discussed. And, by using the user-customized function, these bond-graph models are registered to OHC-Sim, and the simulation of dynamic characteristics of a pneumatic circuit is carried out.

Approximate computing in general has garnered much needed attention in the design community owing to high power saving benefits, and at the same time quick generation of results. Approximate computing as a design technique continues to offer design advantages which is recently ceased by the ever decreasing technology scaling. Approximate computing is mostly applied to arithmetic designs, that has resulted in significant research interests. The paper proposes a reliable and efficient approximate multiplier design, that uses optimized lower part constant OR adder (OLOCA) design and hardware optimized approximate adder with normal error distribution (HOAANED) separately as two variants. The two approximate multipliers derived from OLOCA adder and HOAANED adder were found to be highly power and footprint efficient, and in addition offers performance improvement over other approximate multipliers. The error characteristics for the proposed multiplier designs were evaluated and compared with the existing approximate multiplier design. The proposed multiplier design along with the existing ones were synthesized using 45 nm CMOS technology and results were analyzed. The proposed approximate multipliers were further explored for canny edge detection application, and results for different standard images were found to be highly acceptable showing 99.9% of outcome similar to exact multiplier design.

Approximate computing is an emerging paradigm to improve the efficiency of computing systems by leveraging the intrinsic resilience of applications to their computations being executed in an approximate manner. Prior efforts on approximate hardware design have largely focused on circuit-level techniques. We propose a new approach, clock overgating, for the design of approximate circuits at the Register Transfer Level (RTL). The key idea is to gate the clock signal to selected Flip-Flops (FFs) in the circuit, even during execution cycles in which the circuit functionality is sensitive to their state. This saves power in the clock tree, the FF itself and in its downstream logic, while a quality loss ensues if the erroneous FF state propagates to the circuit output. We develop a systematic methodology to identify an energy-efficient overgating configuration for any given circuit and quality constraint. Towards this end, we develop 3 key strategies --- significance-based overgating, grouping FFs into overgating islands, and utilizing internal signals of the circuit as triggers for overgating --- that efficiently prune the large space of possible overgating configurations. We evaluate clock overgating by designing approximate versions of 6 machine learning accelerators, and demonstrate energy benefits of 1.36× on average (and upto 1.80×) for negligible (<0.5%) loss in application quality (classification accuracy).