A New Approximate 5:2 Compressor for High Accuracy 8-Bit MAC Design

A Wavelet Transform (WT) is a mathematical technique that transforms a signal into different frequency components, each analyzed with a resolution that matches its scale. Wavelets are small waves with limited duration and they possess both time and frequency localization, which means they can capture both high-frequency and low-frequency information simultaneously. There are several types of wavelet transforms, and, depending on the application, one may be preferred to the others. For a continuous input signal, the time and scale parameters can be continuous leading to the Continuous Wavelet Transform (CWT) and Discrete wavelets. Image processing is a critical area in modern computing with applications ranging from medical imaging to remote sensing and computer vision. Traditional Fourier analysis has limitations in capturing localized features in images due to its global nature. Wavelet Transform (WT), with its multi-resolution and localized time-frequency representation, provides a powerful alternative for analysing and processing visual information. This paper presents a comprehensive overview of the theory of wavelet transforms, their mathematical foundations, and applications in image processing and signal processing, including compression of images, denoising and feature extraction from images.

Approximate arithmetic circuits are designed to improve energy efficiency and performance in error-tolerant applications. The approximate arithmetic circuits behave differently for different applications. Also, the approximation may violate basic algebraic properties like commutativity, associativity, identity, etc. The violation of algebraic properties makes the output of the approximate circuits dependent on the order of the inputs. The existing work [1] has been on approximate adders and their application to image addition. This paper investigates the impact of approximation and commutativity in the 12 compressor-based multipliers for image processing applications and CNNs. The first observation is that the accuracy of the neural network drops drastically if the multiplication of zero is approximated. Second, the outcomes of neural networks and error-resilient image processing applications tend to differ depending on the order of the inputs. For instance, when the Yang2 [2] design is implemented on ResNet18, we observe an accuracy of 58.07% for \(a \times b\) and 69.4% for \(b \times a\). Based on our findings, we propose that prior knowledge can be used to organize input data to increase output quality for these applications.KeywordsError-resilienceApproximate computingCompressorsImage processing

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-/spl mu/m double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance.

Image processing is finding it's applications in the various fields like medical electronics, artificial intelligence, entertainment electronics, security systems and many more. Image processing deals with the processing of image signals. Image processing can be done either by analog means or digital means. Widespread use of PCs as development tool, makes the use of PCs attractive. To process images by digital means, it becomes necessary to digitize the analog image signals into digital image. Because of high cost of commercially available video digitizers, image processing applications are limited to only research laboratories. This paper discusses the design of a low cost, medium resolution video digitizer. Performance of this video digitizer is comparable to the commercially available video digitizers.

The development of energy-efficient circuits tailored for error-tolerant applications marks a significant advancement in low-power computing, particularly within the realm of approximate computing. This approach addresses the inherent trade-off between precise computation and computational efficiency. This study introduces a novel energy-efficient multiplier specifically designed for image-processing tasks. Integral to the multiplication process are compressors, which play a crucial role in reducing partial products. Moreover, higher-order approximate compressors, including 7:2 and 8:2 configurations, have been meticulously designed and simulated using Verilog coding within the VIVADO environment. The proposed approximated 7:2, and 8:2 compressors utilize 44%, and 41.37% less area, respectively, 52.35%, and 56.61% low-power consumption, respectively, and 13.73%, and 16.77% high speed, respectively, in comparison to exact compressors comparative analysis reveals that these proposed higher-order compressors offer reduced area requirements and lower power consumption compared to existing state-of-the-art techniques. Incorporating these high-performance compressors at the reduction stage of multipliers yields an energy-efficient circuit tailored for error-tolerant applications. The research employs three distinct designs (Design 1, Design 2 and Design 3), each leveraging the proposed higher-order compressors and approximate adders across varying bit-widths (8-, 16-, 32- and 64-bit). Each design presents unique advantages and limitations, catering to the specific requirements of the application.

In most of the digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. In this paper, design of MAC unit is proposed. The multiplier used inside the MAC unit is based on the Sutra "Urdhva Tiryagbhyam" (Vertically and Cross wise) which is one of the Sutras of Vedic mathematics. Vedic mathematics is mainly based on sixteen Sutras and was rediscovered in early twentieth century. In ancient India, this Sutra was traditionally used for decimal number multiplications within less time. The same concept is applied for multiplication of binary numbers to make it useful in the digital hardware. Here, the coding is done in VHDL and synthesis is done in Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the "Modified Booth Wallace Multiplier" and "High speed Vedic multiplier" presented by Ramesh Pushpangadam. Our proposed Vedic multiplier seems to have better performance.

Wireless Sensor Network (WSN) presents significant challenges for the application of distributed signal processing and distributed control. These systems will challenge us to apply appropriate techniques to construct capable processing units with sensing nodes considering energy constraints. Digital Signal Processing (DSP) is one of the capable processing units, but it is not commonly used in WSN because of the power constraint. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DSP architectures. The MAC unit determines the power and the speed of the overall system; it always lies in the critical path. Developing high speed and low power MAC is crucial to use DSP in the future WSN. In this work, a fast and low power MAC Unit is proposed. The proposed architecture is based on examination of the critical delays and hardware complexities of merged MAC architectures to design a unit with a low critical path delay and low hardware complexity. The new architecture reduces the hardware complexity of the summation network, thus reduces the overall power. Increasing the speed of operation is achieved by feeding the bits of the accumulated operand into the summation tree before the final adder instead of going through the entire summation network. The ASIC implementation of the proposed 32-bit MAC unit saves 5.5% of the area, 9% of the energy, and reduces the delay by 13% compared to the regular merged MAC unit.

The cellular neural/nonlinear network (CNN) is a powerful tool for image and video signal processing, as well as robotic and biological visions. The designs for CNN templates are one of the important issues for the practical applica- tions of CNNs. This paper first describes and proves the local rules of the binary Point Extract (PE) CNN introduced by Roska et al., then extends the PE CNN to a gray similar neighborhood pixel remover (SNPR) CNN. The robust design theorem of the SNPR CNN has been established, using a PE CNN and a SNPR processes several images. The results agree with theoretical predictions. In particular, combining the SNPR CNN with median filtering approach is able to re- move the salt & pepper noise in images.

Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This paper proposes a novel dynamic verification methodology of the AC circuit. The key idea of the proposed methodology is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed methodology additionally embeds the Design Under Test (DUT) mechanisms into the calculation part of computational quality. Thanks to the integration of CGF and DUT mechanism, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed methodology and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed methodology achieves the target coverage three times faster than the random test.

Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This work focuses on the verification where the computational results can be observed, the computational quality can be calculated from computational results, and the constraint of computational quality is given and defined as the constraint which is set to the computational quality of designed AC circuit with given workloads. Then, this paper proposes a novel dynamic verification framework of the AC circuit. The key idea of the proposed framework is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed framework additionally embeds the Design Under Verification (DUV) component into the calculation part of computational quality. Thanks to the DUV integration, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed framework and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed framework achieved 3.85 to 10.36 times higher coverage than the random test.

An image processing system with variety of visual techniques has been designed and implemented to support the detailed analysis of land surface. The strong points of this system are dynamic algorithm-save-method for efficient handling of the huge size image, automatic menu generation and powerful visual programming environment. Most of the existing image processing systems use general graphic user interfaces. The authors adopted visual program language for remotely sensed image processing for its powerful programmability and ease of use. This system is an integrated raster/vector analysis system and equipped with many special functions such as vector overlay, flight simulation, 3D simulation, and object modeling techniques etc. In addition to the modules for image and digital signal processing, the system provides many other utilities such as toolbox, an interactive image editor. This paper also presents several cases of image analysis methods and design concept for visual programming environment.

As power consumption in digital systems grows rapidly, energy efficiency has become a crucial concern. To address this, approximate computing was proposed as an innovative paradigm. In this work, we realize an approximate logic synthesis (ALS) toolchain utilizing Boolean matrix factorization algorithm based on error sharping technique (ESBMF) and open-source tools, its basic operation is to generate the corresponding approximation circuit by different input error thresholds. Moreover, we also present an approximate image signal processor (APPROX-ISP). Compared to the original counterpart, APPROX-ISP achieves area benefits of 44.2%, 36.7%, 34.1%, 34.5%, power consumption benefits of 49.9%, 38.6%, 37.1%, 52.2%, and delay benefits of 57.6%, 34.9%, 51.0%, 19.5% using 12-bit Adder, 14-bit Adder, 15-bit Adder and 8-bit Multiplier, respectively. Our experiment demonstrates that there is almost no accuracy degradation in machine learning tasks while using APPROX-ISP.

. The development of an Image Processing (IP) application is a complex activity, which can be greatly alleviated by user-friendly graphical programming environments. Our major objective is to help IP experts reuse parts of their applications. A first work towards knowledge reuse has been to propose a suitable representation of the strategies of IP experts by means of IP plans (trees of tasks, methods and tools). This paper describes the CBR module of our interactive system for the development of IP plans. After a brief presentation of the overall architecture of the system and its other modules, we explain the distinction between an IP case and an IP plan, and give the selection criteria and functions that are used for similarity calculation. The core of the CBR module is a search/adaptation algorithm, whose main steps are detailed: retrieval of suitable cases, recursive adaptation of the selected one and memorization of new cases. The system’s implementation is presently completed; its functioning is described in a session showing the kind of assistance provided by the CBR module during the development of a new IP application.

This paper illustrates the implementation of Multiply-Accumulate unit (MAC) to improve performance using the Ancient Indian Vedic Mathematics. Real-time signal processing needs high speed and high yield Multiplier-Accumulator (MAC) unit that consumes less power, which is always a key to achieve a high performance digital signal processing system. Speed of the multiplier is essential to MAC unit. Vedic Mathematics is the ancient mathematics. There are sixteenth unique sutras in the Vedic mathematics. The Sutras saves effort and time required in solving the problems as compared to the formal methods. The Sutra “Urdhav Triyagbhyam” (Vertical and Crosswise) is used inside the MAC unit as a multiplier. The coding is done in VHDL, synthesis is done in Xilinx ISE series and the FPGA synthesis is done using Xilinx Spartan library. The results show that design of MAC unit using Vedic multiplication is much more efficient in terms of delay and speed compared to conventional multiplication.

Often as the most important arithmetic modules in a processor, adders, multipliers, and dividers determine the performance and energy efficiency of many computing tasks. The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition, and data analytics), have driven the development of approximate arithmetic design. In this article, a review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers, and dividers. A comprehensive and comparative evaluation of their error and circuit characteristics is performed for understanding the features of various designs. By using approximate multipliers and adders, the circuit for an image processing application consumes as little as 47% of the power and 36% of the power-delay product of an accurate design while achieving similar image processing quality. Improvements in delay, power, and area are obtained for the detection of differences in images by using approximate dividers.