A run-time modulo scheduling by using a binary translation mechanism

The authors describe a genetic algorithm for a difficult optimisation problem which arises in the context of parallel processing. The problem is to assign each task in the given task graph T to a processor, so as to minimise the total overall execution time of the tasks. Total execution time is computed with the knowledge of individual run times of tasks and the communication requirements among tasks. The intertask communication time is dependent on the interconnection network which connects the processors. No prior knowledge of the interconnection topology is assumed. The algorithm finds the interconnection architecture that is best suited for the task graph T; this makes sense when the target architecture is reconfigurable through programmable switches, e.g. transputer based parallel processors. The algorithm is also extended to add heterogeneous platforms, where each task t can be executed on a particular class of processors. The optimisation technique is based on the genetic paradigm. The authors describe an efficient chromosome representation, genetic operators and a fitness measure suitable for the application.

Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approach increasingly suffers from large execution times. In this paper, we propose a more efficient formulation of the modulo scheduling space that significantly decreases the execution time of solvers based on integer linear programs. For example, the total execution time is reduced by a factor of 8.6 when 782 loops from the Perfect Club, SPEC, and Livermore Fortran Kernels are scheduled for minimum register requirements using the more efficient formulation instead of the traditional formulation. Experimental evidence further indicates that significantly larger loops can be scheduled under realistic machine constraints.

Communication in a parallel system frequently involves moving data from the memory of one node to the memory of another; this is the standard communication model employed in message passing systems. Depending on the application, we observe a variety of patterns as part of communication steps, e.g., regular (i.e. blocks of data), strided, or irregular (indexed) memory accesses. The effective speed of these communication steps is determined by the network bandwidth and the memory bandwidth, and measurements on current parallel supercomputers indicate that the performance is limited by the memory bandwidth rather than the network bandwidth.Current systems provide a wealth of options to perform communication, and a compiler or user is faced with the difficulty of finding the communication operations that best use the available memory and network bandwidth. This paper provides a framework to evaluate different solutions for inter-node communication and presents the copy-transfer model; this model captures the contributions of the memory system to inter-node communication. We demonstrate the usefulness of this simple model by applying it to two commercial parallel systems, the Cray T3D and the Intel Paragon.In particular we identify two methods to transfer data between nodes in these two machines. In buffer-packing transfers, a contiguous block of data is transferred across the network. If the data are not stored contiguously, they are copied to (gathering) or from (scattering) buffers in local memory before and after the transfer. Chained transfers perform gathering, transfer and scattering in one step, reading the data elements with some non-sequential pattern and immediately transferring them on to the destination.Our model and measurements indicate that chaining of the gather, transfer, and scatter operations results in better performance than buffer packing for many important access patterns. Most standard message passing libraries (like MPI, PVM or NX) force the parallelizing compiler (or the programmer) to employ the buffer-packing communication operations. However, the addition of hardware support dedicated to communication (e.g., DMAs, line-transfer units) now gives the compiler a wider range of options.

The performance of modern processors is often limited by execution stalls resulting from long memory access latencies. Compile-time optimizations, deep cache hierarchies and prefetching mechanisms already provide significant performance gains, by performing memory accesses in parallel with computation. However, they are reaching a throughput improvement limit. Hence, new solutions that effectively exploit the memory access patterns to improve processing throughput are required. To achieve this objective, a new compiler-assisted data streaming method is proposed. It leverages static analysis and code transformations with an on-chip data streaming support as a viable alternative to prefetching mechanisms for regular code structures. Static analysis is used to identify and encode memory accesses with a dedicated representation. Then, a code transformation algorithm detaches data indexation and address calculation from computation, allowing for a significant code reduction. An on-chip data stream controller, attached to the L1 data cache, is used to autonomously generate memory accesses from the pattern representation and reorganize the data transfers in streams, with the aid of stream buffers. When compared with state-of-the-art prefetchers, the proposed solution provides up to 26 percent of code reduction, an IPC improvement of 2.4x, and an average performance improvement of 40 percent.

With the increase in the volume of container trading, automated container terminals have gradually become the target of the world’s largest port construction. In order to improve the efficiency of the automated AGV container terminal and gantry cranes, the possible conflicts in the horizontal AGV transportation area under different load conditions and speeds have been resolved. The problem is to create a comprehensive scheduling model that minimizes the total AGV execution time through prediction and solved by genetic algorithm. Experimental data analysis shows that after optimization, the total execution time and conflict timeout of multiple AGVs are reduced, which improves the work efficiency of AGVs.

Ant colony optimization is an evolutionary approach where a number of ants search for good solutions. Ant Algorithms often show good optimization results. This paper, discusses number of algorithms built using modified ant colony algorithm which are used to solve the problem of assigning each task in a given task graph to a processor in a reconfigurable multi processor architecture so as to minimize the total overall execution time of the tasks. Each group of ants is working collectively to find the interconnection architecture best suited for the task graph and the best scheduling of that task graph on the chosen interconnection architecture. The total execution time is computed according to the knowledge of individual run times of tasks and the communication requirements among tasks. The inter task communication time is dependent on the interconnection processor architecture. The results of using modified ant colony algorithm in reconfigurable parallel processor system are compared with that of using genetic algorithm for solving the same problem.

The increasing interest in adopting cloud technologies for Industry 4.0 and mixed-criticality environments is paving the way for compelling new opportunities and challenges. However, cloud deployments use multicore processors that introduce interference between co-executing applications on different cores due to contention in shared resources, such as the memory subsystem. Such interference can cause critical applications to miss their deadlines.To enable the co-execution of critical and non-critical applications on the same multicore processor, we propose an approach that guarantees memory access time isolation for critical cores, while not jeopardizing the memory bandwidth of the non-critical ones. We prove the viability of our approach using Intel’s resource director technology for memory access detection and regulation. Experiments show that queue occupancy is an excellent metric to estimate the number of interfering cores co-accessing the memory. We also assess the indirect memory bandwidth limitation achievable by applying Intel’s Memory Bandwidth Allocation technology.

We studied an efficient software implementation of H.264/AVC sub-pixel motion estimation (ME) algorithm on a VLIW-SIMD digital signal processor, TMS320C6416. The sub-pixel ME algorithm demands large memory accesses while the required arithmetic operations are fairly simple. Although the CPU clock cycles for arithmetic operations can be reduced much by employing sub-word operations and applying software pipelining techniques, the limited memory bandwidth of the architecture restricts the overall performance. Moreover, aggressive VLIW-SIMD optimization results in the degradation of the performance by causing excessive CPU stalls during memory accesses. In this paper, we relieved the memory bandwidth requirements for creating quarter-pixel images by reducing the precision of image data, from 8 bits to 4 bits. As a result, the amount of memory accesses is much reduced at the cost of some increase of the arithmetic operations, which contributes to the balance of arithmetic and memory access operations. The experimental result shows that the memory stall cycles are decreased by 80% and the speed-up of 260% is obtained. The bit rate of the encoded video stream is increased slightly, about 2% on the average, due to the effects of quantization.

Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently access the data beyond the allocated buffers or access buffers that were already freed. Such programs and OSs may run for years before their problems can be detected because improper memory accesses frequently result in a silent data corruption. Not surprisingly, most computer worms exploit buffer overflow errors to gain complete control over computer systems. Only after recent worm epidemics, did code developers begin to realize the scale of the problem and the number of potential memory-access violations in existing code.Due to the syntax and flexibility of many programming languages, memory access violation problems cannot be detected at compile time. Tools that verify correctness before every memory access impose unacceptably high overheads. As a result, most of the developed techniques focus on preventing the hijacking of control by hackers and worms due to stack overflows. Consequently, hidden data corruption is given less attention.Memory access violations can be efficiently detected using the hardware support of the paging and virtual memory.Kefence is the general run-time solution we developed that allows to detect and avoid in-kernel overflow, underflow, and stale access problems for internal kernel buffers. Kefence is especially applicable to file system code because file systems operate at a high level of abstraction and require no direct access to the physical memory. At the same time, file systems use a large number of kernel buffers and file system errors are most harmful for users because users' persistent data can be corrupted.

Domain-specific accelerators for graph analytics leverage a large on-chip memory in order to tackle the intensive random memory accesses, offering higher performance and energy efficiency than conventional architectures. However, limited by the inefficient usage of on-chip memory, current accelerators suffer from energy and performance bottlenecks due to the large amount of off-chip memory accesses. In this work, we introduce an online preprocessing step for the vertex-centric programming model based on our observation of imbalanced memory bandwidth utilization between two execution phases. Our scheme improves energy efficiency and performance by significantly reducing off-chip accesses in two ways. First, we sequence random off-chip memory accesses to balance memory bandwidth demands and improve the utilization of on-chip memory. Second, we prune active leaf vertices to avoid redundant memory accesses. We evaluate our method on a state-of-the-art graph analytics accelerator and achieve 1.6× speedup while reducing energy consumption by 42% on average. © 2019 IEEE.

As the gap between processor performance and memory latency widens, the computer architecture research area is always out for new solutions for efficient memory access. In this paper, we analyze the maximum achievable gain by simulating an ideal DRAM memory that always services requests as row buffer hits, thus minimizing memory access latency and queuing. We reproduced the state-of-the-art ConGen2 technique from Natale et al. to measure how much improvement is still available. ConGen2 minimizes row buffer misses according to a min-k-cut solution based on all memory accesses of a target application. We observed that ConGen2 improves memory usage by 2.30% on average, while the ideal memory gains 36.88% on average for the chosen benchmarks. This gap leaves a wide margin of benefits to be gained.

Currently many researches focus on new methods of accelerating memory accesses between memory controller and memory modules. However, the absence of an accelerator for memory accesses between CPU and memory controller wastes the performance benefits of new methods. Therefore, we propose a coordinated batch method to support high concurrency of memory accesses (HCMA). Compared to the conventional method of holding outstanding memory access requests in miss status handling registers (MSHRs), HCMA method takes advantage of scratchpad memory in FPGAs or SoCs to circumvent the limitation of MSHR entries. The concurrency of requests is only limited by the capacity of scratchpad memory. Moreover, to avoid the higher latency when searching more entries, we design an efficient coordinating mechanism based on circular queues.We evaluate the performance of HCMA method on an MP-SoC FPGA platform. Compared to conventional methods based on MSHRs, HCMA method supports ten times of concurrent memory accesses (from 10 to 128 entries on our evaluation platform). HCMA method achieves up to 2.72× memory bandwidth utilization for applications that access memory with massive fine-grained random requests, and to 3.46× memory bandwidth utilization for stream-based memory accesses. For real applications like CG, our method improves speedup performance by 29.87%.

Grid system is used by many researchers’ and scholars all over the world to solve the complicated and complex problems in different sciences. Job ranking backfilling is the most used model by many researchers in grid system to improve the performance of job scheduling algorithm. The model aims on serving the smallest job in the queue. As a second improvement of job backfilling, researchers proposed job ranking backfilling that serve job based on ranking equation. This paper proposes an enhance job ranking algorithm based on using linear and logarithmic ranking equations. Both proposed ranking equations used curve estimation model to predict on the variables’ coefficients. By simulation and after different tests, the average results of job ranking backfilling with linear ranking equation outperform conventional job ranking backfilling with improvement equal 3.2% and 56.53% in total execution time and average waiting time, respectively. In addition, job ranking backfilling with logarithmic ranking equation shows average improvement equal 1.78% and 46.62% in total execution time and average waiting time, respectively. The results indicate that the proposed ranking equations would improve conventional job ranking backfilling in high and low demand grid system under different conditions

Quadratic Assignment Problem (QAP) is one of the most difficult combinatorial problems in the literature and has a diverse field of applications. This paper presents the results of experiments on the impact of parallelization of a sequential GA using island model. Both of the genetic algorithms are applied to the QAP. For the island model parallel GA, we systematically change the number of islands and investigate the effects of dividing the same global population into a number of subpopulations. The number of islands is gradually increased to observe the effects on solution quality and speedup in total execution time using different problem instances. The results clearly indicate that, while parallelized version outperforms sequential counterpart in both solution quality and total execution time, an increasing number of subpopulations also positively effects the results until a critical point where every subpopulation has a certain number of individuals to be able to evolve independently. Beyond that point, the performance of the algorithm begins to decrease.

NVIDIA GPUDirect is a family of technologies aimed at optimizing data movement among GPUs (P2P) or between GPUs and third-party devices (RDMA). GPUDirect Async, introduced in CUDA 8.0, is a new addition which allows direct synchronization between GPU and third party devices. For example, Async allows an NVIDIA GPU to directly trigger and poll for completion of communication operations queued to an InfiniBand Connect-IB network adapter, removing CPU involvement from the critical path in GPU accelerated applications. In this paper, we present the building blocks of GPUDirect Async and explain the supported usage models of this new technology. We also present a performance evaluation using a micro-benchmark and a synthetic stencil benchmark. Finally, we demonstrate the use of Async in a few multi-GPU MPI applications: HPGMG-FV (geometric multi-grid), achieving up to 25% improvement in total execution time; CoMD-CUDA (classical molecular dynamics), reducing communications times up to 30%; LULESH2-CUDA, achieving an average performance improvement of 13% in the total execution time.