Efficient formulation for optimal modulo schedulers

Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for the highest steady state throughput and minimum register requirements. Our method determines optimal register requirements for machines with nite resources and for general dependence graphs. We compare the performance of this and other modulo schedulers for a benchmark of 629 loops from the Perfect Club, SPEC-89, and the Livermore Fortran Kernels. Measurements demonstrate the potential of register-sensitive modulo schedulers, which will be useful in evaluating the performance of register-sensitive modulo scheduling heuristics.

This study aimed to kinematically compare the Yop Chagi execution between novice and experienced university Taekwondo practitioners, focusing on movement efficiency. Forty university students were allocated into two groups: Novice (n = 20; ≤6 months experience) and Experienced (n = 20; ≥3 years of competitive experience). Participants performed maximal effort side kicks targeting a pad at trochanter height. Movement was captured using two high-speed cameras (120 Hz). Kinematic variables included hip and knee joint angles at peak flexion/extension, peak angular velocities, linear velocity of the foot, and total kick execution time. Between-group differences were analysed using independent t-tests or Mann-Whitney U tests, with effect sizes (Cohen's d) reported. The experienced group demonstrated significantly larger hip abduction and knee flexion angles during the chamber phase (p < 0.01, d > 0.8), and greater knee extension at the point of impact (p < 0.01, d = 1.2) compared to novices. The experienced group also exhibited superior performance in peak hip and knee angular velocities (p < 0.01, d > 1.5), resulting in a 28% higher peak linear velocity of the foot (p < 0.001, d = 2.1). Furthermore, the total execution time was significantly shorter for the experienced group (p < 0.01, d = 1.4). Experienced practitioners execute the Yop Chagi with a more efficient kinematic pattern, characterized by a larger range of motion, faster segmental velocities, and reduced execution time. These findings suggest that long-term training optimizes the proximal-to-distal kinematic sequence, enhancing kick performance.

Minimizing executing and transmitting time of task scheduling and resource allocation in C-RANs

With the increase in the volume of container trading, automated container terminals have gradually become the target of the world’s largest port construction. In order to improve the efficiency of the automated AGV container terminal and gantry cranes, the possible conflicts in the horizontal AGV transportation area under different load conditions and speeds have been resolved. The problem is to create a comprehensive scheduling model that minimizes the total AGV execution time through prediction and solved by genetic algorithm. Experimental data analysis shows that after optimization, the total execution time and conflict timeout of multiple AGVs are reduced, which improves the work efficiency of AGVs.

The authors describe a genetic algorithm for a difficult optimisation problem which arises in the context of parallel processing. The problem is to assign each task in the given task graph T to a processor, so as to minimise the total overall execution time of the tasks. Total execution time is computed with the knowledge of individual run times of tasks and the communication requirements among tasks. The intertask communication time is dependent on the interconnection network which connects the processors. No prior knowledge of the interconnection topology is assumed. The algorithm finds the interconnection architecture that is best suited for the task graph T; this makes sense when the target architecture is reconfigurable through programmable switches, e.g. transputer based parallel processors. The algorithm is also extended to add heterogeneous platforms, where each task t can be executed on a particular class of processors. The optimisation technique is based on the genetic paradigm. The authors describe an efficient chromosome representation, genetic operators and a fitness measure suitable for the application.

Ant colony optimization is an evolutionary approach where a number of ants search for good solutions. Ant Algorithms often show good optimization results. This paper, discusses number of algorithms built using modified ant colony algorithm which are used to solve the problem of assigning each task in a given task graph to a processor in a reconfigurable multi processor architecture so as to minimize the total overall execution time of the tasks. Each group of ants is working collectively to find the interconnection architecture best suited for the task graph and the best scheduling of that task graph on the chosen interconnection architecture. The total execution time is computed according to the knowledge of individual run times of tasks and the communication requirements among tasks. The inter task communication time is dependent on the interconnection processor architecture. The results of using modified ant colony algorithm in reconfigurable parallel processor system are compared with that of using genetic algorithm for solving the same problem.

It is well known that innermost loop optimizations have a big effect on the total execution time. Although CGRAs is widely used for this type of optimizations, their usage at run-time has been limited due to the overheads introduced by application analysis, code transformation, and reconfiguration. These steps are normally performed during compile time. In this work, we present the first dynamic translation technique for the modulo scheduling approach that can convert binary code on-the-fly to run on a CGRA. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated (from one memory access per cycle to two memory accesses per cycle). Moreover, a comparison to the state-of-the-art static compiler-based approaches for inner loop accelerators has been done by using CGRA and VLIW as target architectures. Additionally, to measure area and performance, the proposed CGRA was prototyped on a FPGA. The area comparisons show that crossbar CGRA (with 16 processing elements) is 1.9x larger than the VLIW 4-issue and 1.3x smaller than a VLIW 8-issue softcore processor, respectively. In addition, it reaches an overall speedup factor of 2.17x and 2.0x in comparison to the 4 and 8-issue, respectively. Our results also demonstrate that the runtime algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for an n-issue VLIW processor.

This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >

This paper addresses the problem of estimating the total execution time of a parallel program based on a domain decomposition strategy.When the execution time of each processor may vary, the total execution time is non deterministic, specially if the communication to exchange boundary data is asynchronous.We consider the situation where a single iteration on each processor can take two different execution times. We show that the total time depends on the topology of the interconnection network and provide a lower bound for the ring and the grid.This analysis is supported further by a set of simulations and comparisons of specific cases.KeywordsExecution TimeDomain DecompositionBubble SizeTotal DelayDomain Decomposition MethodThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper proposes a customized implementation of Mini-Mips processor; commencing from Register Transfer Level (RTL) down to GDSii Layout level. The implementation is customized for a string matching specific-application that is given problem for second Iranian National Digital Systems Design contest 2015 at Amirkabir University of Technology. We apply various techniques to make reasonable trade-off between area, delay, and power consumption ranging from loop unrolling in algorithm level to low power techniques such as clock gating in circuit level. Moreover, we utilize compiler optimization techniques to reduce the execution time. Our simulations show that execution time is reduced more than 63% on average. In overall, we come up with an optimized design in terms of chip area, power consumption and total execution time.

This paper describes an automatic data distribution method which deal with both the alignment and the distribution problems in a single optimization phase, as opposed to sequentially solving these two inter-dependent approaches as done by previous work. The core of this work is called the Communication-Parallelism Graph, which describes the relationships among array dimensions of the same and different array references regarding communication and parallelism. The overall data distribution problem is then formulated as a linear 0–1 integer programming problem, where the objective function to be minimized is the total execution time. The solution is static in the sense that the layout of the arrays does not change during the execution of the program. We also show the feasibility of using this approach to solve the problem in terms of compilation time and quality of the solutions generated.

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling.We propose Moovac1, a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution.We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger.Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation.Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of small- to medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

Probabilistic models are receiving increasing attention as a complementary alternative to more widespread machine learning approaches such as neural networks. One particularly interesting class of models, so-called Sum-Product Networks (SPNs), combine the expressiveness of probabilistic models with tractable inference, making them an interesting candidate for use in real-world applications. Previously, inference in SPNs has successfully been accelerated by fully pipelined FPGA-based hardware. However, with these approaches, the maximum size of the SPN for FPGA acceleration has effectively been limited by the fully spatial mapping of arithmetic operations into hardware and the number of available resources in the FPGA. In this work, we present an extended and specialized modulo scheduling algorithm based on Integer Linear Programming (ILP) for time-multiplexed sharing of hardware arithmetic operators in the SPN inference accelerator. In addition and in order to scale the scheduling to large SPN graphs, we combine the scheduling algorithm with a graph-partitioning heuristic, exploiting the graph structure of SPNs. The combination of heuristic graph partitioning and ILP-based scheduling allows generating pipelined accelerators with the best possible initiation interval, while limiting the resource utilization to pre-set bounds. The evaluation discusses the effect different parameters have on convergence time and solution quality. A performance comparison shows that the FPGA improves the inference throughput over a comparable CPU- and GPU platform by a factor (geo.-mean) of 4.4x and 1.7x, respectively.

Benchmarking is a widely used approach to measure computer performance. Current use of benchmarks only provides running times to describe the performance of a tested system. Glancing through these execution times provides little or no information about system strengths and weaknesses. A novel benchmarking methodology is proposed to identify key performance parameters; the methodology is based on measuring performance vectors. A performance vector is a vector of ratings that represents delivered performance of primitive operations of a system. In order to measure performance vectors, a geometric model is proposed which defines system behavior using the concepts of support points, context lattice, and operating points. In addition to the performance vector, other metrics derivable from the geometric model include the variation in system performance and the compliance of benchmarks. Using this methodology, the performance vectors of the Sun SuperSPARC (desktop workstation) and the Cray C90 (vector supercomputer) are evaluated using the SPEC benchmarks and the Perfect Club, respectively. The proposed methodology respects several practical constraints and issues in benchmarking. The instrumentation required is minimal. The benchmarks used are realistic (not synthetic) in order to reflect the delivered (not peak) performance. Finally, operations in the performance vector are not measured individually since there may be significant interplay in their executions.

Cloud data centers, realizing that the amount of unused resources is significant, have started offering them as transient resources with unpredictable, irreversible revocation. The use of transient resources indicates many relevant issues still pose critical challenges, including security, strong and reliable connectivity and fault-tolerance approaches. To effectively use transient cloud servers to fulfill user requests, it is necessary to define an appropriate fault-tolerant mechanism and its respective parameters to avoid data loss if an unexpected failure occurs. We present an agent-based framework, namely BRA2Cloud, for integrating bag-of-tasks enabled systems using unreliable transient resources. To guarantee application execution and better use of idle resources, it is necessary to create an execution plan through fault tolerance definitions to increase reliability. To do this, BRA2Cloud agents combine features to predict failures in a multi-agent architecture that dynamically creates fault-tolerant multi-strategies, considering the current availability scenario and providing a resilient environment according to users’ application needs. Our approach was validated using real data retrieved between 2017 and 2019 from Amazon Spot Instances. Exhaustive experiments achieved high accuracy levels, reaching a 91% survival prediction success rate, which indicates the model is effective under realistic working conditions. We consider the results promising, decreasing up to 74.48% in total execution time when compared to other approaches in the literature. As the main requirements of our proposal, we have defined a series of features that BRA2Cloud should have in order to address the impact of these definitions on resiliency provision, application execution time reduction, and monetary cost reduction.