Optimum modulo schedules for minimum register requirements

Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approach increasingly suffers from large execution times. In this paper, we propose a more efficient formulation of the modulo scheduling space that significantly decreases the execution time of solvers based on integer linear programs. For example, the total execution time is reduced by a factor of 8.6 when 782 loops from the Perfect Club, SPEC, and Livermore Fortran Kernels are scheduled for minimum register requirements using the more efficient formulation instead of the traditional formulation. Experimental evidence further indicates that significantly larger loops can be scheduled under realistic machine constraints.

Module scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a module reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive module scheduling and is useful in evaluating the performance of lifetime-sensitive module scheduling heuristics.

Modulo scheduling is a software pipelining technique exploiting instruction-level parallelism (ILP) of VLIW architectures to efficiently implement loops. This paper presents a novel enumeration-based resource-constrained heuristic for modulo scheduling. It takes into consideration the criticality of the nodes, generating near optimal schedules in terms of initiation intervals and register requirements. The scheduling algorithm outperformed better-known heuristics in terms of the quality of schedules, while presenting small compilation time enabling it to be used in a production environment. Experimental results on the VLIW TMS320C6678 DSP processor, showed improved performance on a signal processing set of algorithms.

This paper analyzes the competitive effects of regulatory minimum capital requirements on an oligopolistic loan market. Before competing in loan rates banks choose their capital structure, thereby making an imperfect commitment to a loan capacity. It is shown that due to this imperfect commitment, regulatory requirements not only increase the marginal cost of loan supply, but can also have a collusive effect resulting in increased profits. This paper derives the threshold value from which capital requirements can turn one round Bertrand competition into a two‐stage interaction with capacity commitment, leading to Cournot outcomes. Therefore, it provides theoretical support for the applicability of the Cournot approach when modeling imperfect loan competition.

Modulo scheduling is an effective instruction scheduling technique for exploiting ILP in modern microprocessors with wide machine resources. As with any instruction scheduling technique, its effectiveness is constrained by both the source program dependencies as deduced by the compiler and the resources available in the target machine. Data speculation is a technique for eliminating memory dependencies in the instruction dependence graph with demonstrated benefits in acyclic scheduling. Therefore, by applying data speculation in modulo scheduled loops we are able to achieve higher degrees of instruction level parallelism. This paper addresses a number of key issues in applying data speculation to modulo scheduling: effectively identifying the additional instructions required to recover from mis-speculation, ensuring full recoverability of instructions speculated across multiple stages and possibly executed speculatively multiple times on-the-fly, and coloring rotating registers for speculated instructions and instructions in recovery blocks. We implemented the framework proposed in this paper and demonstrated its effectiveness through experimental results.

Recently, several systems based on reconfigurable logic have been designed and built. These systems permit arbitrary digital logic functions to be configured in hardware. This ability to dynamically configure such circuits promises to provide the flexibility of a software based system with the performance of custom hardware. This dissertation proposes a high level language approach to programming reconfigurable logic based machines. This approach uses a data parallel variant of the Clanguage. To support this high level language approach, a novel reconfigurable logic device is described. These devices are in turn interfaced to a memory system and used to perform computation. To demonstrate the validity of this approach, several computationally intensive algorithms are implemented and simulated. Among these algorithms are cellular automata, image processing, neural networks, the Mandelbrot set and the Fourier transform. In addition, selected portions of the Livermore FORTRAN kernels are simulated. Estimates of performance and required system resources are reported for each algorithm.

A configuration for a high-performance dataflow processor is proposed. The processor is equipped with a matching unit that allows multiple-token matching operations to proceed concurrently. Performance of the processor is evaluated through simulation with Livermore Fortran kernels, both vectorizable and non vectorizable, as a workload. Compared to the existing system, the proposed processor shows a substantial speedup. >

Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore's law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes. Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer. Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.

This chapter discusses legislative changes and public policy ideas affecting plan distribution, and is divided into two main section sets. The first set presents and examines recent legislative and regulatory requirement changes affecting plan distribution. In particular, it explains the changing rules for lump-sum calculations for distributions from pension plans, joint-and-survivor annuities, fiduciary obligations on sponsors of plans with annuities, and minimum distribution requirements affecting life annuities. The second and final set of sections, on the other hand, outlines a variety of public policy ideas in this area, and evaluates their pros and cons.

This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, we propose a new organization of the register file in order not to affect cycle time and also reduce area, while increasing the number of registers. This can be useful to minimize the frequency of spill at a reasonable cost. The spill code can increase the minimum initiation interval and decrease loop performance. This new organization consists of a small high bandwidth multiported register file and a low bandwidth port-limited register file called sack. A mechanism to assign values to the sack is presented. We demonstrate the effectiveness of our approach by experimenting with a collection of loops from the Perfect Club benchmark suite. Experiments in order to find the optimal number of registers into the sack have been done. We also measured the effect of the spill code on loop performance.

Capital Regulation for Position Risk in Banks, Securities Firms and Insurance Companies

This paper provides guidelines to identify all threats and assess a pipeline’s susceptibility to those threats in order to select appropriate and effective mitigation, monitoring, and prevention measures prior to reactivating pipelines. The intent of this paper is to provide pipeline operators, consultants and regulatory agencies with a generic threat assessment approach that has to be customized to the pipeline-specific characteristics and conditions, and the regulatory requirements of its own jurisdiction. A literature review and authors’ experiences across the pipeline industry have identified the need for a generic, yet complete approach that guides pipeline integrity engineers in the methodologies that adequately and effectively assess threats prior to reactivation and that can be validated in a timely manner during the operations. Pipeline operators may be called on to reactivate pipelines that are facing challenges such as aging, changes in operational conditions, lack of maintenance and inconsistent integrity practices while facing constraints from increasing population density, higher pressure and flow throughput requirements of a competitive marketplace, and regulatory requirements insisting on higher levels of safety and protection of the environment. This paper was structured with the following components to assist the reader in conducting threat assessments: • Current regulations and recognized industry standards with respect to reactivating pipelines; • Definition of and differentiation between hazard and threat; • Hazard identification analysis for the known and potential situations, events and conditions; and • Threat susceptibility and identification analysis process for the known categories derived from the hazard identification process. A case study is described as an example of applying the guidelines to conduct threat susceptibility and identification assessments of a pipeline prior to its reactivation. The results from the threat susceptibility and identification assessment process can help operators, consultants and regulators in determining effective inspection, mitigation, prevention and monitoring measures.

Under the Revised International Capital Framework, debtors’ credit ratings and probabilities of default in credit portfolios have a key role in determining minimum regulatory capital requirements. To measure discriminatory power of rating systems, methods such as the area under a ROC curve, the Accuracy Ratio and PowerStat are often used both in academic studies and in practice. This paper shows that these measures need to be interpreted with caution since their values hinge crucially on the characteristics of the portfolio under consideration and not just on the quality of the rating system.

Chapter 2 - What Is “Capital” Management?

Are non-risk based capital requirements for insurance companies binding?