A scheduling algorithm for multiport memory minimization in datapath synthesis

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections. Consequently, we try to minimize the cost of interconnections first and then to group the variables to form memory modules later. For a number of benchmark problems, it has been shown that this approach is quite effective.

At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new approach to the allocation of multiport memories which minimizes hardware costs in ASIC datapath synthesis. The proposed approach, AMD, considers not only the access requirements of registers but also the lifetime of registers. The objective is to minimize the requirement of registers and multiport memory modules under a given resource constraints simultaneously. The minimization problem has been modeled as a 0-1 integer linear programming problem. This approach is illustrated with an example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In order to optimally allocate multiport memories in datapath synthesis, registers are simultaneously assigned to a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. The LP model is extended, and a fast heuristic approach that searches for an allocation is presented. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. The designer specifies a range of design parameters, and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. The components of this system are described, and some examples of its use are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Grouping variables into multiport memories is an essential step for multiport memory based data path synthesis. The proposed system, GMD, not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem is formulated as a 0-1 integer linear programming (ILP) problem. Experiments on benchmarks are promising. >

In Static List Scheduling (SLS), initially the ALAP (As Late As Possible) algorithm is performed, followed by ASAP (As Soon As Possible) algorithm. The time interval for control steps and successor selection are the vital drawback of ASAP algorithm. Hence, in this paper, the optimized scheduling algorithm is proposed for High Level Synthesis (HLS), where the ALAP in SLS is followed by Force Directed Scheduling (FDS). The proposed scheduling algorithm is implemented in Icarus Verilog and targeted in ZC7020 FPGA board. The proposed optimized scheduling algorithm is evaluated in terms of control steps and resource utilization. The evaluation is carried out for various benchmarks such as, EW Filter, IIR filter, FIR filter, AR filter and Discrete Cosine Transform (DCT). The achieved results in terms of the control steps and resource utilization (i.e. LUT and Flip-flop) shows the proposed optimized scheduling algorithm outperforms the conventional Static List Scheduling (SLS) algorithm.

This paper proposes a novel class of wavelength scheduling algorithms in optical burst switching networks. The proposed wavelength scheduling algorithms process a batch of data bursts together instead of processing them one by one. When a control burst with a reservation request arrives to a batch scheduler, the scheduler waits for a small amount of time, called the acceptance delay, before deciding to accept or reject the reservation request. After the acceptance delay has passed, the scheduler processes all the reservation requests that have arrived during the acceptance delay, then it accepts the requests that will maximize the utilization of the wavelength channels. We describe an optimal batch scheduler that serves as an upper bound on the performance of batch scheduling algorithms. Furthermore, we introduce four novel heuristic batch scheduling algorithms. The bursts of the proposed algorithms is evaluated using a discrete-event simulation model. Simulation results suggest that batch schedulers could decrease the blocking probability by 25% compared the best previously known wavelength scheduling algorithm.

Previously proposed wavelength scheduling algorithms in optical burst switching networks process each reservation request individually and in a greedy manner. In this paper we propose a new family of wavelength scheduling algorithms that process a batch of reservation requests together instead of processing them one by one. When a control burst with a reservation request arrives to a free batch scheduler, the scheduler waits for a small amount of time, called the acceptance delay, before deciding to accept or reject the reservation request. After the acceptance delay has passed, the scheduler processes all the reservation requests that have arrived during the acceptance delay, then it accepts the requests that will maximize the utilization of the wavelength channels. We describe an optimal batch scheduler that serves as an upper bound on the performance of batch scheduling algorithms. Furthermore, we introduce two heuristic batch scheduling algorithms. The performance of the proposed algorithms is evaluated using a discrete-event simulation model. Simulation results suggest that batch schedulers could decrease the blocking probability by 25% compared to the best previously known wavelength scheduling algorithm.

The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ..., p-port faults. In addition, the paper discusses the test procedure for such memories; it shows that the time complexity of the required tests is not exponential proportionally with p, as published by different authors, but it is linear, irrespective of the number of ports of which the multiport memory consists.

A new evolutionary algorithm for scheduling and allocation algorithm is developed for an elliptic filter. The elliptic filter is scheduled and allocated in the proposed work which is then compared with the different scheduling algorithms like As Soon As Possible algorithm, As Late As Possible algorithm, Mobility Based Shift algorithm, FDLS, FDS and MOGS. In this paper execution time and resource utilization is calculated using different scheduling algorithm for an Elliptic Filter and reported that proposed Scheduling and Allocation increases the speed of operation by reducing the control step. The proposed work to analyse the magnitude, phase and noise responses for different scheduling algorithm in an elliptic filter.

In typical optical burst switching (OBS) networks a reservation request is either accepted or rejected as soon as it is presented to the employed wavelength scheduling algorithm. This paper proposes a class of wavelength scheduling algorithms that process a batch of data bursts together instead of processing them one by one. When a control burst with a reservation request arrives to a free batch scheduler, the scheduler waits for a small amount of time, called the acceptance delay, before deciding to accept or reject the reservation request. After the acceptance delay has passed, the scheduler processes all the reservation requests that have arrived during the acceptance delay period, then it accepts the requests that maximizes the utilization of the wavelength channels. We describe an optimal batch scheduler that serves as an upper bound on the performance of batch scheduling algorithms. Furthermore, we introduce two novel heuristic batch scheduling algorithms. Simulation results suggest that batch schedulers could decrease the blocking probability by 25% compared to the best previously known wavelength scheduling algorithm

A unified algorithm is presented to solve the problem of estimation and scheduling for performance constrained data flow graphs. The algorithm achieves superior results by first computing a lower bound on the number of functional units required to satisfy the performance constraint T, and then scheduling the operations into the best control steps using the lower bound algorithm. The lower bound not only greatly reduces the size of the solution space, but also provides a means to measure the proximity of the final solution to an optimal one. Our algorithm is the first one to use a sharp lower bound estimation technique to direct scheduling. In addition, our unified algorithm can easily be incorporated into a branch-and-bound algorithm to solve the scheduling problem optimally. Since our algorithm computes a sharp lower bound, the computation time of an optimal algorithm can be greatly reduced. Experiments indicate that our scheduling algorithm can produce results very close to the lower bound. For all of the test cases the difference between our upper and lower bounds is not greater than one.

Reconfigurable computing refers to the notions of configware and flowware. Configware means structural programming, or programming in space to execute computation in space. Flowware means dataflow programming that schedules the data flow for output from or input to the configware architecture. In this paper, data flows of a synthesized computation are formalized. This means that data flow is specified as a behavioral stream function in stream calculus, which is used to underpin the semantics for Register Transfer Level (RTL) synthesis. A stream representation allows the use of coinductive principles in stream calculus. In particular, using the coinductive proof principle, we show that behavioral stream functions in the three-stage synthesis process (scheduling, register allocation and binding, allocation and binding of functional units) are always bisimilar regardless of changes in a scheduling, allocation or binding procedure. Our formalization makes pipelining possible, in which all functional units as well as registers of hardware resources are reused during different control steps (C-steps). Moreover, a coinductive approach to verifying flowware synthesis, which is independent of the heuristic during register allocating and binding step, is proposed as a practical technique.

A versatile scheduling algorithm has been developed as part of the BRIDGE synthesis system. This algorithm schedules the various operations in the given sequential behavioral description into a designer-specified number of control steps. Scheduling is performed by computing the attraction forces for each operation to each control step. A novel concept of sharing forces is used to increase multifunction functional unit utilization. These sharing forces are determined by performing look-ahead on functional unit allocation. With the scheduler, the designer can systematically explore the design space by controlling the number of control steps. Estimates of operation delay times are used to drive the synthesis. Experimental results were obtained by synthesizing the entire design all the way to the gate level and measuring the transistor count (to approximate area) and by measuring the critical path delay using a timing analyzer. Results show an increase in functional unit utilization because of the sharing forces used. The results also show that the size of the controller and the path delay in the controller cannot be ignored in exploring design trade-offs. Some other interesting results are reported. >

Asymmetric multicore processors (AMPs) have been proposed as an energy-efficient alternative to symmetric mul-ticore processors (SMPs). However, AMPs derive their performance from core specialization, which requires co-running applications to be scheduled to run on their most appropriate core types. Despite extensive research on AMP scheduling, developing an effective scheduling algorithm remains challenging. Contention for shared resources is a key performance-limiting factor, which often renders existing contention-free scheduling algorithms ineffective. We introduce a contention-aware scheduling algorithm for ARM's big.LITTLE, a commercial AMP platform. Our algorithm comprises an offline stage and an online stage. The offline stage builds a performance interference model for an application by training it with a set of co-running applications. Guided by this model, the online stage schedules a workload by assigning its applications to their most appropriate core types in order to minimize the performance degradation caused by contention for shared resources. Our model can accurately predict the performance degradation of an application when co-running with other applications with an average prediction error of 9.60%. Compared with the default scheduler provided for ARM's big.LITTLE and the speedup-factor-driven scheduler, our contention-aware scheduler can improve overall system performance by up to 28.32% and 28.51%, respectively.

ProcSimity is a software tool that supports research in processor allocation and scheduling for highly parallel systems. ProcSimity's multicomputer simulator supports experimentation with selected allocation and scheduling algorithms on architectures with a range of network topologies and for several current routing and flow control mechanisms. Message-passing can be simulated in detail at the flit level or at a higher level of modeling. Our tool supports both stochastic job streams as well as communication patterns from actual parallel applications, including several of the NAS parallel benchmarks. ProcSimity's visualisation and performance analysis tool allows the user to view a dynamic animation of the selected algorithms as well as a variety of system and job level performance metrics. ProcSimity has been successfully used in experiments investigating the feasibility of non-contiguous processor allocation in meshes and k-ary n-cubes. >