Optimal allocation of multiport memories in datapath synthesis

At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new approach to the allocation of multiport memories which minimizes hardware costs in ASIC datapath synthesis. The proposed approach, AMD, considers not only the access requirements of registers but also the lifetime of registers. The objective is to minimize the requirement of registers and multiport memory modules under a given resource constraints simultaneously. The minimization problem has been modeled as a 0-1 integer linear programming problem. This approach is illustrated with an example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we present a new scheduling algorithm that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps, and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. When compared with previous approaches for several benchmarks available from the literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections. Consequently, we try to minimize the cost of interconnections first and then to group the variables to form memory modules later. For a number of benchmark problems, it has been shown that this approach is quite effective.

Grouping variables into multiport memories is an essential step for multiport memory based data path synthesis. The proposed system, GMD, not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem is formulated as a 0-1 integer linear programming (ILP) problem. Experiments on benchmarks are promising. >

A multiport memory allocation problem for hierarchical, i.e. multi-dimensional, data streams is described. Memory allocation techniques are used in high level synthesis for foreground and background memory allocation, the design of data format converters, and the design of synchronous inter-processor communication hardware. The techniques presented in this paper differ from other approaches in the sense that data streams are considered to be design entities and are not expanded to individual samples. A formal model for hierarchical data streams is given and a memory allocation algorithm is presented. The algorithm comprises two steps: data routing and assignment of signal delays to memories. A number of sub-problems are formulated as ILP programs. In the presented form, the allocation algorithm only considers interconnect costs, but memory size and other cost factors can be taken into account. The presented work is implemented in the memory allocation tool MEDEA which is part of the PHIDEO synthesis system.

A new algorithm named the time-zone algorithm for solving register allocation problem in the automatic data path synthesis is presented in this paper. The time-zone algorithm was developed from the left-edge algorithm with which the number of registers can be minimized. The time-zone algorithm was developed to minimize the number of registers as well as the interconnections and the number of multiplexers required for the registers. The experimental results obtained from testing several published examples show that the interconnections are improved and the number of multiplexers is reduced while at the same time the number of registers is still minimized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Rate control typically involves two steps: bit allocation and bitrate control. The bit allocation step can be implemented in various fashions depending on how many levels of allocation are desired and whether or not an optimal rate–distortion (R-D) performance is pursued. The bitrate control step has a simple aim in achieving the target bitrate as precisely as possible. In our recent research, we have developed a $ {\lambda }$ -domain rate control algorithm that is capable of controlling the bitrate precisely for High Efficiency Video Coding (HEVC). The initial research showed that the bitrate control in the $ {\lambda }$ -domain can be more precise than the conventional schemes. However, the simple bit allocation scheme adopted in this initial research is unable to achieve an optimal R-D performance reflecting the inherent R-D characteristics governed by the video content. In order to achieve an optimal R-D performance, the bit allocation algorithms need to be developed taking into account the video content of a given sequence. The key issue in deriving the video-content-guided optimal bit allocation algorithm is to build a suitable R-D model to characterize the R-D behavior of the video content. In this paper, to complement the R- $ {\lambda }$ model developed in our initial work, a D- $ {\lambda }$ model is properly constructed to complete a comprehensive framework of $ {\lambda }$ -domain R-D analysis. Based on this comprehensive $ {\lambda }$ -domain R-D analysis framework, a suite of optimal bit allocation algorithms are developed. In particular, we design both picture-level and basic-unit-level bit allocation algorithms based on the fundamental R-D optimization theory to take full advantage of the content-guided principles. The proposed algorithms are implemented in HEVC reference software, and the experimental results demonstrate that they can achieve an obvious R-D performance improvement with a smaller bitrate control error. The proposed bit allocation algorithms have already been adopted by the Joint Collaborative Team on Video Coding and integrated into the HEVC reference software.

Fair Welfare Maximization

In this paper, we study the memory allocation problem in data path synthesis. We propose a register organization called circular FIFO as an alternative to register file organization. In comparison with register file organization, FIFO organization eliminates the overhead of address generation and decoding hardware. The memory allocation problem, based on the circular FIFO organization, has been solved efficiently using constraint logic and interval constraint programming.

A computationally efficient optimal discrete bit allocation algorithm is proposed for medium and high target bit rate discrete multitone (DMT) transmissions. Unlike conventional greedy bit-loading algorithms, which compare the incremental transmission power of multicarriers bit-by-bit and allocate one bit at a time, the proposed algorithm is based on parallel bit-loading with reference to a virtual equal power assignment bit allocation. After maximum bit rate allocation, the algorithm achieves the target bit rate by two types of parallel bit- loading. If the target bit rate allocation is not optimal, bit swapping is performed to obtain the optimal solution. Simulation results using the standard asymmetric digital subscriber line (ADSL) test loops demonstrate the reduced computational load of the proposed algorithm compared to the existing optimal discrete bit allocation algorithm when the target rate is between 60% and 99% of the loop's maximum bit rate.

In this paper, we present an energy-per-bit minimized radio resource allocation scheme in heterogeneous networks equipped with multi-homing capability, simultaneously connecting to different wireless interfaces. Specifically, we formulate an optimization problem related to minimization of energy-per-bit which takes a form of nonlinear fractional programming. Then we derive a parametric optimization problem out of that fractional programming and solve the original problem by using a double-loop iteration method. In each iteration, we derive the optimal resource allocation policy by applying Lagrangian duality and an efficient dual update method. In addition, we present suboptimal resource allocation algorithms using the properties of the optimal resource allocation policy. Numerical results reveal that the optimal allocation algorithm improves energy efficiency significantly over the existing resource allocation algorithms designed for homogeneous networks and its performance is superior to suboptimal algorithms in reducing energy consumption as well as in enhancing network energy efficiency.

New design and mapping of sonochemical reactor operating at capacity of 72L

The primary adult type hypolactasia is the most common form of genetically determined disaccharidase deficiency. This study examined a large and homogeneous population of the south of Italy: surgical biopsy specimens of proximal jejunum from 178 adult subjects have been assayed for disaccharidase activities; the expression of lactase protein and lactase activity has also been investigated on tissue sections by immunomorphological and enzymohistochemical techniques. Histograms of lactase to sucrase ratio were found to provide a useful distribution of the lactase activity; a lactase to sucrase ratio of 0.17 was found to show discrimination between tissues with persistence of high lactase activity and tissues with adult type hypolactasia. In all 28 subjects with persistent high lactase activity, a uniform distribution of lactase protein and lactase activity in all villus enterocytes was detected, whereas in all 150 subjects with adult type hypolactasia a variable number of villus enterocytes failed to express the lactase. Moreover in hypolactasic samples the lactase activity on tissue sections was constantly detected later than in samples with persistent high lactase activity. The absolute correlation between the immunohistochemical and enzymohistochemical features and the assessment of lactase activity in intestinal homogenates suggests that the morphological criteria are an alternative method for the diagnosis of adult type hypolactasia in human biopsy specimens from proximal small jejunum.

Changes in the activity of superoxide dismutase (SOD), ascorbate peroxidase (APX), and catalase (CAT) for the plants Nicotiana tabacum L. and Secale cereale L. during low-temperature hardening have been investigated. It was determined that a transient increase in the content of MDA occurs in tobacco plants at the beginning of the hardening period with subsequent activation of SOD, APX, and CAT. Unlike tobacco, winter rye has an MDA content and activity of SOD, APX, and CAT throughout the hardening period that remains at the level of unhardened plants. In tobacco cells, the majority of SOD activity was detected in chloroplasts (90%), while other cellular structures accounted for only 10% of the total activity identified in PAGE. In winter rye cells, SOD activity was distributed evenly between chloroplasts and other cellular compartments (46% in chloroplasts and 54% outside of chloroplasts). The distribution of APX and CAT activity in tobacco and winter rye cells was identical: all APX was concentrated in chloroplasts, while all catalase activity was manifested outside of chloroplasts. It is concluded that tobacco and winter rye plants showed different antioxidant defense strategies under conditions of low hardening temperatures. Tobacco plants provided protection against oxidative damage during low-temperature hardening by increasing activity of SOD, APX, and CAT. Winter rye plants were able to avoid the development of oxidative stress during hardening due to uniform distribution of SOD activity in cells, maintaining the constitutive activity of SOD, APX, and CAT, and, probably, due to the accumulation of nonenzymatic antioxidants.

Carrier aggregation (CA) technique has been adopted by 3GPP LTE-Advanced due to its ability of enhancing the spectrum efficiency and peak data rates through aggregating multiple component carriers (CCs). Two main factors make power control optimization very essential for CA-MIMO radio link: the different channel characteristics in multiple CCs, and multiple power constraint conditions (per-CC, per-antenna and pertransmitter power constraints) in the actual CA system deployment. This paper firstly derives the degenerate conditions of optimal power allocation for a single-transmitter CA-MIMO system. Stemming from the derived degenerate conditions, we propose a modified hybrid gradient optimal power allocation(MHGOPA) algorithm to maximize the system performance. Simulation results verify the validity of the proposed resource allocation approach by comparing with baseline average power allocation algorithm. Finally, we extend the MHGOPA algorithm into a heterogeneous CA network with multiple transmitters working simultaneously.