A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single- or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

Design for Testability (DFT) based on scan and ATPG has been adopted as a reliable and broadly acceptable methodology that provides very high test coverage, but for large circuits, the growing test data volume causes a significant increase in test cost because of much longer test time and elevated tester memory requirements. Test compression or scan compression provides great reduction in test data volume and test time required by adding on-chip decompressor and compactor. In this paper comparative analysis are made for Broadcast, XOR decompressor along with XOR, MISR and Hybrid compactors with respect to test coverage, test cycles required and test data volume by considering Flash Interface as CUT. From the experiments, it is observed that XOR decompressor with MISR compactor architecture provides 17.31% to 49.76% reduction in test data volume compared to other architectures, with 99.76% of fault coverage, 16694 test cycles and 2104µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of area overhead.

In this paper, we present a selective scan slice encoding technique for power-aware test data compression. The proposed scheme dramatically reduces test data volume via scan slice repetition, and generates an adjacent-filled test pattern known as the favorable low-power pattern mapping method. Experiments were performed on the large ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we propose a virtual circuit model to make the linear de-compressor transparent to the external testing. As a result, existing X-filling methods can be reused to reduce test power. Experimental results on benchmark circuits demonstrate the effciency of the proposed approach.

Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem; and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger ISCAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.

We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.

During last decade, IEEE standard 1687 or IJTAG has been utilized to test the embedded instruments on chips that support test and measurement applications. Recently, IJTAG has been incorporated into the newly developed testing architecture referred as a Streaming Scan Network (SSN) for efficient testing of the complex System-on-Chips (SoCs). IJTAG registers are used to configure the components of a Streaming Scan Host (SSH) node associated with each core in the SSN network. SSN supports packetized test data distribution for streaming of the test data through SSN bus. SSN provides efficient SoC testing by several times reduction in test time and test data volume with limited pin count. Although SSN outshines in providing testing benefits, it lacks security support. An unauthorized user can maliciously modify the configuration registers and extracts sensitive information. Presence of untrusted modules in the network also amplifies the security concerns as each packet may contain test data of multiple cores. Hence, an untrusted cores can simply sniff the data destined for other cores. Therefore, to address the security issues in SSN test architecture, one needs to protect the system against internal untrusted third-party intellectual property (3PIP) modules and unauthorized users. This work discusses the security vulnerabilities of SSN architecture by demonstrating an attack scenario. Keeping the flexibility of SSN intact, we propose a modified SSH architecture and an authorization unit to ensure security against data sniffing attacks and unauthorized accesses, respectively. A state-of-the-art scheme is compared against the proposed approach in terms of area overheads. Thus, this paper presents a multi-level methodology with very low area and testing overheads for secure SSN.

Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the random access scan (RAS) scheme offers a solution to alleviate the above problems (Baik et al., 2004). In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, test response abundant, constrained static compaction, and bit propagation before test vector dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.

Nowadays System on Chip (SoC) is expected to perform a large number of applications as per the requirement of customers. Increase in the number of applications leads to an increase in the number of cores inside the SoC. Customers want to use a large number of applications in their product but in a cheap price. In this price competitive market, the manufacturer can not increase the price above a certain range in order to sustain in the market. It is decisive to have a high-quality product with the low price. Testing each core thoroughly can require high amount of time and increases the test economics. Hence it is better to cover significant faults only and test the cores partially. In this paper, we propose a method for incomplete testing of the SoC cores, which recedes Test Power (TP) and Test Data Volume (TDV). Our method persists significant fault coverage and tests most of the significant faults. We also propose a power aware Test access mechanism (TAM) architecture compatible with the reduced test vectors. It provides a trade-off between quality of product and testing parameters (i.e., TP, TDV). Results from experiments exhibit an effective reduction in TDV, TP with a nominal compromise on the quality of testing.

Test data compression is based on storage of compressed tests and use of on-chip decompression logic for test application. Further reductions in the input test data volume are achieved by methods that apply several different tests based on every compressed test. This article makes the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit. This article studies such an approach for path delay faults (PDFs) using a linear-feedback shift register (LFSR) as the decompression logic. Because of the nature of PDFs, targeting an extended subset of PDFs increases the confidence that important PDFs are detected. However, the benefit of detecting additional faults may not justify an increase in the number of stored tests. The approach suggested in this article is used for detecting an extended subset of target PDFs using the same set of LFSR seeds. Extra clocking of the LFSR is used for obtaining scan-in states for several new two-cycle tests based on the same seed. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.