A sigma-delta based PLL for non-sinusoidal waveforms

In this paper we present the design flow for a fractional-N (frac-N) frequency synthesizer proto type from the system level conceptualization of the PLL to its hardware implementation. The prototyping hardware consists of a of frac-N PLL IC designed in TSMC 0.18 mum mixed signal/RF CMOS process mounted on a RF prototype impedance controlled board. The RF board is interfaced to a digital delta sigma modulator (DSM) realized in a Xilinx FPGA on a commercial evaluation board. Matlab was employed for the system level PLL design. The TSMC 0.18 mum CMOS Process Design Kit was used for the frac-N IC realization. Verilog HDL was used for the implementation of the DSM in the FPGA. With an FPGA based DSM platform, prototypes for different communication modulation formats, and for different DSM topologies, different order integrators, and different dithering schemes can be evaluated quickly and economically. We elaborate on our software selection for the design flow in the University environment. In addition to discussing the prototype design methodology, we present the simulated and measured results for the MASH-11 and MASH- 12 frac-N synthesizers. The prototype encompassed all possible aspects of a complex hardware system design: an IC design, RF board design, board-to-board interface issues and the Verilog coding of DSMs in an FPGA. This process served as a useful tool for learning the various aspects of RF hardware design.

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

The speed at which a digital sigma-delta modulator can operate is limited by the latency of the loop filter. A digital sigma-delta modulator is presented which overcomes the problem of long adder carry propagation delays. The design is sixth order and implemented using a single pipelined resonator section. >

Higher Order Digital Delta-Sigma Modulator with Small Fluctuation: Sliding Mode Operation Approach

Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This can happen for a range of constant and periodic inputs. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can produce spurs in the output spectrum. We call pseudorandom dithering effective if it breaks up periodic cycles in the modulator without producing its own spurs in the output spectrum. This paper presents rigorous mathematical analysis and a design methodology to achieve effective dithering.

In-phase and quadrature-phase (IQ) sinusoidal signals are used as bases functions in many phase modulation schemes in communication systems. Generating such signals in engineering education laboratories without higher-end signal generators is quite challenging. Most of the time, the IQ signals used in undergraduate engineering education laboratories are in audio frequency range that is used to demonstrate or experiment with various phase modulation schemes. This paper presents a method to generate IQ sinusoids in the audio frequency range using direct digital synthesis technique. The system developed is simulated using MathWorks® Simulink and implemented on commonly available Xilinx’s® Spartan 6 FPGA. The system designed is capable of producing phase correct sine and cosine waves having frequencies between 1 Hz and 20 kHz.

Phase feedback and adjustment between wireless nodes greatly reduce the power efficiency of distributed beamforming. In this paper, we propose a distributed transmit beamforming method without any phase feedback between nodes. The concept of our approach is to have the received signals retrace their ways, so that the phase offset of the forward path compensates that of the backward path; as a result, signals from different nodes in-phase combine at the destination. Therefore, the received power or the communication range is increased. In order to implement the concept of "retracement", we also propose a transceiver prototype which is based on the Direct Digital Synthesis technique. Experimental and simulation results validate the effectiveness of our approach.

In this paper, we propose a low-cost arbitrary waveform generator to simulate battery voltage transients specified by ISO 16750–2 voltage profiles. The proposed methodology is based on the technique of direct digital synthesis (DDS) implemented in a microcontroller. The proposed approach allows reducing the amount of Flash memory used by the lookup table. The device generates several types of waveforms and uses a sequencer to combine them into the desired voltage profile. For testing purposes, emulations of the variations on the cranking voltage and the superimposed A.C. voltage are used to validate the proposed solution.

The technique of direct waveform synthesis (DWS) is analyzed based on the technique of direct digital synthesis (DDS). The digital modulated waveforms are created by lookup tables (LUT) which contain waveform samples precomputed using the DWS technique. A novel DWS technique is proposed whose carrier frequency is programmable compared to the current one. Furthermore, the effect of memory versus computation is performed. The simulation results show that it is an efficient scheme to implement the software radio modulation for the DWS technique especially the novel technique of DWS with carrier frequency programmability.

Mathematical calculation of sequence length in LFSR-dithered MASH digital delta-sigma modulator with odd initial condition

A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer

A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the ...

A frequency synthesizer is designed in a 0.25 /spl mu/m CMOS process for 5-GHz WLAN applications. In consideration of low power consumption, the synthesizer integrates a low power and high efficient voltage-controlled oscillator (VCO) and an injection-locked frequency divider as the first stage prescaler. A digital delta-sigma modulator is used for frequency switching control where the pipelining technique is adopted to enhance the modulator performance. The synthesizer has a bandwidth of 300 KHz for a 35 MHz reference and can achieve a close-in phase noise of about -80 dBc/Hz while the total power consumption is 33 mW from a single 2.5 V supply.

A digital delta-sigma modulator using the one-hot residue number system (OHRNS) is presented. It exhibits a large oversampling ratio (OSR) in comparison with equivalent binary designs. Its second-order architecture employs a two-stage cascade structure with two-level internal and four-level output quantization. It is intended for use in a high-resolution interpolative digital-to analog converter. Analytical estimates show a significant improvement in OSR and latency over binary-number system-based designs. These benefits are made possible by the use of the (OHRNS), which allows addition and multiplication to be performed equally quickly and simply, using barrel shifters and signal transposition. An application specific integrated circuit (ASIC) implementation of the design is also presented in a 2-/spl mu/m CMOS technology.