Complexity and Power Reduction in Digital Delta-Sigma Modulators

Higher Order Digital Delta-Sigma Modulator with Small Fluctuation: Sliding Mode Operation Approach

In this paper we present the design flow for a fractional-N (frac-N) frequency synthesizer proto type from the system level conceptualization of the PLL to its hardware implementation. The prototyping hardware consists of a of frac-N PLL IC designed in TSMC 0.18 mum mixed signal/RF CMOS process mounted on a RF prototype impedance controlled board. The RF board is interfaced to a digital delta sigma modulator (DSM) realized in a Xilinx FPGA on a commercial evaluation board. Matlab was employed for the system level PLL design. The TSMC 0.18 mum CMOS Process Design Kit was used for the frac-N IC realization. Verilog HDL was used for the implementation of the DSM in the FPGA. With an FPGA based DSM platform, prototypes for different communication modulation formats, and for different DSM topologies, different order integrators, and different dithering schemes can be evaluated quickly and economically. We elaborate on our software selection for the design flow in the University environment. In addition to discussing the prototype design methodology, we present the simulated and measured results for the MASH-11 and MASH- 12 frac-N synthesizers. The prototype encompassed all possible aspects of a complex hardware system design: an IC design, RF board design, board-to-board interface issues and the Verilog coding of DSMs in an FPGA. This process served as a useful tool for learning the various aspects of RF hardware design.

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

The speed at which a digital sigma-delta modulator can operate is limited by the latency of the loop filter. A digital sigma-delta modulator is presented which overcomes the problem of long adder carry propagation delays. The design is sixth order and implemented using a single pipelined resonator section. >

디지털 입력 D급 증폭기는 보청기에서 사용되고 있으며 D급 증폭기는 디지털 회로와 아날로그 회로로 구성되어진다. 아날로그 회로는 가청 주파수 대역에서 잡음을 억제하고 디지털 입력을 아날로그 신호로 변환한다. 본 논문에서 제안한 인터폴레이티드 디지털 델타-시그마 변조기는 디지털 신호 처리기의 출력 신호를 D/A 변조기 입력에 적합하도록 데이터를 변조시킨다. 디지털 필터는 16-bit, 25-kbps 펄스 코드 변조 신호를 16-bit, 50-kbps 신호로 보간 작업을 한다. 이 보간 필터 출력은 3차 디지털 델타-시그마 변조기를 통하여 노이즈 쉐이핑(noise shaping) 처리된다. 최종적으로, 1.5-bit, 3.2-Mbps 신호가 D/A변조기 입력으로 인가된다.

A digital delta-sigma modulator using the one-hot residue number system (OHRNS) is presented. It exhibits a large oversampling ratio (OSR) in comparison with equivalent binary designs. Its second-order architecture employs a two-stage cascade structure with two-level internal and four-level output quantization. It is intended for use in a high-resolution interpolative digital-to analog converter. Analytical estimates show a significant improvement in OSR and latency over binary-number system-based designs. These benefits are made possible by the use of the (OHRNS), which allows addition and multiplication to be performed equally quickly and simply, using barrel shifters and signal transposition. An application specific integrated circuit (ASIC) implementation of the design is also presented in a 2-/spl mu/m CMOS technology.

Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This can happen for a range of constant and periodic inputs. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can produce spurs in the output spectrum. We call pseudorandom dithering effective if it breaks up periodic cycles in the modulator without producing its own spurs in the output spectrum. This paper presents rigorous mathematical analysis and a design methodology to achieve effective dithering.

The purpose of this paper is to modeling and computer simulation of optimized GUI-based system-level design of Sigma Delta Modulator (SDM) based analog-to-digital converter (ADC) in which a top-down approach of designing is mainly focused to improve the resolution of single-loop continuos-time sigma delta because system-level simulation is an important part of system design and can help to estimate power consumption and noise analysis accurately. The presented GUI for the noise calculation and transistor level circuit design and output simulation of Sigma delta modulator based ADC along with its various components like operational trans-conductance amplifier (OTA), Analog-to-Digital converter (ADC), Digital-to-Analog converter is well taken care here to achieve optimized performance. The simulation results show performance of modulator in transistor level and circuit design that are compatible with each other where output was generated successfully in transistor level circuit design along with its waveforms.GUI (Graphical User Interface) allows us to calculate the noise parameters and power consumption parameters. The resolution of modulator is mainly affected by the noise parameters as thermal noise, clock jitter noise, and slew rate of amplifiers, quantization noise, which leads for consumption of power. The modulators offers phase margin 92.84°, gain bandwidth product of 31.89 kHz, Unity gain bandwidth of 1.2295 kHz, That consuming power of 1.430 mW. Even with the high order of modulator, the complexity increases and the device get bulky. When the technology reduces there is possibility for improvement and getting good results. Thus, the CT ∑∆ modulator architecture is well designed and implemented using Tanner EDA tool and with the help of GUI the noise and power consumption parameters have been analyzed.

We study end-to-end quantization in digitally controlled MHz-range GaN DC–DC converters, spanning the analog-to-digital converter (ADC), fixed-point controller, and digital pulse-width modulator (DPWM). A simulation framework sweeps ADC and DPWM resolutions across buck, boost, and inverting buck–boost converters at 1, 5, and 10 MHz, reporting regulation bias, output ripple, and limit-cycle occurrence. A simple metric ρ compares the DPWM step (mapped to V_out) to the ADC least-significant bit and accurately predicts the onset of limit cycles: designs with ρ≥1 avoid limit cycles in all surveyed cases. The results yield practical rules: boost and buck–boost require finer DPWM than buck due to larger ∂V/∂D; dithering and first-order sigma–delta (ΣΔ) modulation provide roughly one to two effective DPWM bits at 1 MHz; and increasing switching frequency tightens timing margins but can be offset by modest DPWM resolution or reduced digital delay. Validation includes analytic–simulated slope agreement, ρ–versus–limit-cycle slices, and robustness to parasitic spreads, ADC noise, and jitter. These findings provide concise, quantitative guidance for selecting ADC and DPWM resolutions to meet ≤10–20 mV ripple targets without limit cycles in MHz GaN converters.

PurposeThe purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approachA low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.FindingsCompared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.Originality/valueComparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

Several integrated capacitors can be used in analog-to-digital converters (ADCs) for complementary-metal-oxide-semiconductor (CMOS) image sensors, including metal-insulator-metal (MIM), metal-oxide-metal (MOM) and metal-oxide-semiconductor (MOS) capacitors. Among those capacitors, MOS capacitors have the highest capacitance density per unit area but a large voltage dependency, which will cause the non-linearity of ADCs. Recently, several types of ADCs are employed for column-parallel ADCs, including a single-slope (SS), sigma-delta (ΔΣ), successive approximation (SAR) ADC, cyclic ADC and folding-integration/cyclic (FI-Cyclic) ADCs. A Cyclic ADC is well known for its ability to achieve medium resolution while requiring a small silicon area and implementing a reasonable conversion rate of one conversion cycle per bit of resolution. Compared with other ADCs, the cyclic ADC has superiority in overcoming the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise and HDR. On the basis of inheriting the advantage of cyclic ADC, FI-Cyclic ADC has better performance on low noise, high grayscale resolution and resulting high dynamic range.

Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.

The sigma–delta analog-to-digital converter (ADC) has less consumption of circuit power and can achieve higher resolution. In this chapter, a sigma–delta ADC which contains a second-order sigma-delta modulator is presented. The modulator architecture is first designed by using the behavioral simulation of MATLAB, and then the TSMC 0.18 μm single-poly six-metal process. Layout of each analog block has been shown. Simulation results show that, with an input of a −6 dB 1 kHz sine, the delta-sigma ADC can achieve an SNR of 87.2 dB. The core size is 0.6456 mm × 0.3340 mm. With a 16-bit resolution, it is suitable for audio applications.

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.