Modeling and System-Level Computer Simulation Approach for Optimization of Single-Loop CT Sigma Delta ADC

This paper is devoted to the discussion of a new kind of sigma-delta modulator as signal expression, by which the higher-bit input signal can be represented as a lower-bit digital signal. The quantized noise shaping and noise frequency spectrum are discussed and compared with the conventional sigma-delta modulator. The theoretic analysis shows that the new modulator is stable. A kind of DDC based on this modulator is designed and simulated.

Sigma-delta ACD has two main parts: analog modulator and digital filter, the performance of modulator determines the performance of sigma-delta ADC, so the design of modulator is very important. The paper introduces the principle of sigma-delta AD modulator with high accuracy and the applied over sampling technique, noise shaping technique and multi-bit quantizer technique. Determining the design scheme of modulator—three bits three orders CIFF(Cascade of integrators, feed forward form) structure, and it makes the behavior level verification for this scheme by Simulink tool in MATLAB. The simulation result shows that multi-bit quantizer modulator can get very high SNR, and based on this result it designs every part of the modulator circuit.

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM, which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Multistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed, which balances the requirements of tone-free and maximum operation frequency.

This paper presents the design of a low-power, medium-resolution, high-speed pipelined analogue-to-digital converter (ADC). A low-power front-end track-and-hold amplifier (THA) is realised to reduce sampling time uncertainty error. The paper also includes the design of low-power, high-bandwidth, high-gain operational transconductance amplifiers (OTAs). The OTAs are used in ADC to reduce finite OTA gain and OTA settling time non-linearity errors. Low power circuit techniques are employed to minimise overall power consumption of the ADC. The proposed ADC is implemented in 180 nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB/57.9 dB, spurious-free dynamic range of 89 dB/86.6 dB and effective number of bits of 9.64-bits/9.33-bits at sampling speed of 50 MHz with the input signal frequencies of 4 MHz/Nyquist frequency. The peak differential-non-linearity of the converter is 0.28/-0.17 LSB and integral-non-linearity of the converter is +0.42/-0.41 LSB. The proposed 10-bit, 50 MS/sec pipelined ADC consumes 24.5 mW amount of power from 1.8 V supply.

This paper presents an elaborate plan and optimization method for designing and implementing low-order band pass digital sigma-delta modulator with high order output dynamic range (DR). The noise suppression in the pass band region of the modulator and high order output DR would be achieved by designing and optimizing the Noise Transfer Function (NTF) based on over sampling ratio (OSR) and desired modulator operational frequency and designing the Signal Transfer Function (STF) by the mean which the optimum gain in desired frequency would be acquired. Designed and optimized modulator has been implemented completely on digital circuits and it would be shown that the first order designed modulator has the output dynamic range of 90dB which corresponds to 15 bits data conversion. Results from various simulations illustrate both the stability and high performance of the design and flexibility of the overall structure.

The sigma–delta analog-to-digital converter (ADC) has less consumption of circuit power and can achieve higher resolution. In this chapter, a sigma–delta ADC which contains a second-order sigma-delta modulator is presented. The modulator architecture is first designed by using the behavioral simulation of MATLAB, and then the TSMC 0.18 μm single-poly six-metal process. Layout of each analog block has been shown. Simulation results show that, with an input of a −6 dB 1 kHz sine, the delta-sigma ADC can achieve an SNR of 87.2 dB. The core size is 0.6456 mm × 0.3340 mm. With a 16-bit resolution, it is suitable for audio applications.

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.

While various circuit noise sources, such as thermal noise, shot noise or 1∕f noise, have a physical origin, other types of noise, like quantization or roundoff noise, occur as a consequence of computational operations performed by circuits. Specifically, the digitization of bandlimited signals with analog-to-digital converters (ADCs) involves not only signal sampling in time, but also amplitude quantization. The quantization operation introduces an error, which is called quantization noise. This noise plays an important role in analyzing the performance of DSP systems and in ADC design. Bennett observed in 1948 that for a sufficiently small discretization step, quantization noise can be viewed approximately as uniformly distributed and white. In a comprehensive study of quantization noise, Widrow was able to derive precise conditions for these properties to hold. Unfortunately, because it is a function of the input signal, the quantization noise is not independent from the input, which creates undesirable artifacts in audio systems. To overcome this problem, an independent dithering noise can be added to the input signal and removed after quantization. This chapter presents a comprehensive analysis of the properties of quantization noise and dithering.

Design and Implementation of Sigma Delta Modulators (ΣΔM) for Class D Audio Amplifiers using Differential Pairs

We propose a cost effective digitized radio-over-fiber (D-RoF) system employing a sigma delta modulation (SDM) and a bidirectional transmission technique using phase modulated downlink and intensity modulated uplink. SDM is transparent to different radio access technologies and modulation formats, and more suitable for a downlink of wireless system because a digital to analog converter (DAC) can be avoided at the base station (BS). Also, Central station and BS share the same light source by using a phase modulation for the downlink and an intensity modulation for the uplink transmission. Avoiding DACs and light sources have advantages in terms of cost reduction, power consumption, and compatibility with conventional wireless network structure. We have designed a cost effective bidirectional D-RoF system using a low pass SDM and measured the downlink and uplink transmission performance in terms of error vector magnitude, signal spectra, and constellations, which are based on the 10MHz LTE 64-QAM standard.

Several integrated capacitors can be used in analog-to-digital converters (ADCs) for complementary-metal-oxide-semiconductor (CMOS) image sensors, including metal-insulator-metal (MIM), metal-oxide-metal (MOM) and metal-oxide-semiconductor (MOS) capacitors. Among those capacitors, MOS capacitors have the highest capacitance density per unit area but a large voltage dependency, which will cause the non-linearity of ADCs. Recently, several types of ADCs are employed for column-parallel ADCs, including a single-slope (SS), sigma-delta (ΔΣ), successive approximation (SAR) ADC, cyclic ADC and folding-integration/cyclic (FI-Cyclic) ADCs. A Cyclic ADC is well known for its ability to achieve medium resolution while requiring a small silicon area and implementing a reasonable conversion rate of one conversion cycle per bit of resolution. Compared with other ADCs, the cyclic ADC has superiority in overcoming the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise and HDR. On the basis of inheriting the advantage of cyclic ADC, FI-Cyclic ADC has better performance on low noise, high grayscale resolution and resulting high dynamic range.

A methodology for the simulation of bandpass continuous time sigma-delta (SigmaDelta) modulators is presented in this paper. This method permits the simulation of SigmaDelta modulators employing continuous-time filters using a fixed-step algorithm. The method is based on the discretization of a continuous-time model and the use of a discrete simulator, which is more efficient than an analog simulator. This transformation is exact in term of noise transfer function and asymptotically exact in term of signal transfer function (the signal transfer function of the model rapidly tends to the continuous time model transfer function when the number of steps increases).

The work focuses on the design of a high speed, low power track-and-hold amplifier (THA) for ten-bit 100 MS/s pipelined analogue-to-digital converter (ADC). A wide bandwidth and high gain two-stage operational transconductance amplifier (OTA) is selected as OTA of THA. This OTA consumes less amount of power and produce less thermal noise. The bootstrap technique is employed to reduce the non-linearity error associated with the input signal. The signal swing of the circuit is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range (DR) of the circuit. The circuit is implemented in UMC 180 nm digital CMOS technology. The THA circuit along with the biasing circuit consumes 5.706 mW power and it achieves 81.23 dB as the spurious free dynamic range (SFDR) for 2 V output at 100 MHz sampling rate. The dynamic range of the THA is 85.94 dB. The proposed THA is simulated using SPECTRE simulator under a variety of process and temperature conditions.

A theoretical analysis of the statistics of the quantization noise in split delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is presented. Sufficient conditions are derived that ensure that the quantization noise components of the constituent DeltaSigma modulators are asymptotically independent of each other, the input, delayed versions of themselves, and uniformly distributed. The application of the conditions is illustrated for two useful classes of split DeltaSigma ADCs.