Quantization Noise and Dithering

Optical communication systems, which operate at very high rates, are limited by the sampling rate bottleneck. The optical wideband regime exceeds analog to digital converters (ADCs) front-end bandwidth. Multi-channel sampling approaches, such as multicoset or interleaved ADCs, have been proposed tho sample the wideband signal using several channels. Each channel samples below the Nyquist rate such that the overall sampling rate is preserved. However, this scheme suffers from two practical limitations that make its implementation difficult. First, the inherent anti-aliasing filter of the samplers distorts the wideband signal. Second, it requires accurate time shifts on the order of the signal's Nyquist rate, which are challenging to maintain. In this work, we propose an alternative multi-channel sampling scheme, based on analog RF demodulation, where each channel aliases the spectrum using a periodic mixing function before integration and sampling. We show that intentionally using the inherent ADC filter to perform integration turns it to an advantage by increasing the signal to noise ratio (SNR). We demonstrate both theoretically and through numerical experiments that our system outperforms multicoset in terms of signal recovery and symbol estimation in the presence of both thermal and quantization noise.

The purpose of this paper is to modeling and computer simulation of optimized GUI-based system-level design of Sigma Delta Modulator (SDM) based analog-to-digital converter (ADC) in which a top-down approach of designing is mainly focused to improve the resolution of single-loop continuos-time sigma delta because system-level simulation is an important part of system design and can help to estimate power consumption and noise analysis accurately. The presented GUI for the noise calculation and transistor level circuit design and output simulation of Sigma delta modulator based ADC along with its various components like operational trans-conductance amplifier (OTA), Analog-to-Digital converter (ADC), Digital-to-Analog converter is well taken care here to achieve optimized performance. The simulation results show performance of modulator in transistor level and circuit design that are compatible with each other where output was generated successfully in transistor level circuit design along with its waveforms.GUI (Graphical User Interface) allows us to calculate the noise parameters and power consumption parameters. The resolution of modulator is mainly affected by the noise parameters as thermal noise, clock jitter noise, and slew rate of amplifiers, quantization noise, which leads for consumption of power. The modulators offers phase margin 92.84°, gain bandwidth product of 31.89 kHz, Unity gain bandwidth of 1.2295 kHz, That consuming power of 1.430 mW. Even with the high order of modulator, the complexity increases and the device get bulky. When the technology reduces there is possibility for improvement and getting good results. Thus, the CT ∑∆ modulator architecture is well designed and implemented using Tanner EDA tool and with the help of GUI the noise and power consumption parameters have been analyzed.

In this paper, we experimentally demonstrated a 2-km high-speed optical interconnection with pulse-shaped pre-equalized four-level pulse amplitude modulation (PAM-4) signal generated by a 3-bit digital-to-analog converter (DAC) with the aid of in-band quantization noise suppression techniques under different oversampling ratios (OSRs) to reduce the influence of quantization noise. The simulation results show that the quantization noise suppression capability of high computational complexity digital resolution enhancer (DRE) is sensitive to taps number of the estimated channel and match filter (MF) response when OSR is sufficient, which will lead to further significant computational complexity increase. To better accommodate this issue, channel response-dependent noise shaping (CRD-NS) which also takes channel response into consideration when optimizing quantization noise distribution is proposed to suppress the in-band quantization noise instead of DRE. Experimental results show that about 2 dB receiver sensitivity improvement can be achieved at the hard-decision forward error correction (HD-FEC) threshold for 110 Gb/s pre-equalized PAM-4 signal generated by 3-bit DAC when the traditional NS technique is replaced by the CRD-NS technique. Compared to the high computational complexity DRE technique, in which channel response is also considered, negligible receiver sensitivity penalty is observed for 110 Gb/s PAM-4 signal, when the CRD-NS technique is utilized. Considering both the system cost and bit error ratio (BER) performance, the generation of high-speed PAM signal with 3-bit DAC enabled by the CRD-NS technique is regarded as a promising scheme for optical interconnection.

This paper presents the design of an ADC (analog to digital converter) applied in a GPS receiver of which the sampling clock is 20 MHz while the input signal is 46 MHz. With the solution of the threshold-limit-speed effect, a comparator with an operating speed of 3 GHz is employed to make the ADC work correctly without S/H circuit. The output signals are quantified both for the sign and magnitude. At the latch output, a buffer working on the clock is used to change the output voltage level to 3.3V while the technology is 0.18-µm CMOS.

The process of converting an analog, or continuous time, signal into a digital signal is known as analog‐to‐digital conversion (ADC). Many signals are inherently analog. Examples of analog signals obtained from a transducer abound. Other analog signals are inherently electrical, such as those obtained from biomedical electromyography or electroencephalography electrodes. In many cases, it is deemed desirable to process a signal by a microprocessor or computer to extract information, or to store the signal in some digital storage medium such as a hard drive, a floppy disk, or a CD ROM. If the original signal is in analog format, in such cases, it is necessary to convert the analog signal into an equivalent digital signal. This article describes the process of ADC. It introduces the topic and describes the operation of two of the most common methods of accomplishing ADC: the successive approximation ADC and the flash ADC. The sampling theorem is stated and proved, aliasing is described, and quantization noise is discussed. Oversampling is described, and the resultant improvements in ADC performance are documented. Then delta‐sigma ADCs are introduced and described. Conventional first‐order and second‐order delta‐sigma ADCs are described and evaluated. Performance comparisons among simple oversampling, first‐order delta‐sigma, and second‐order delta‐sigma ADCs are documented. The article concludes with an example of a higher order delta‐sigma ADC performance evaluation.

This paper presents an analytical study together with an oscillator phase measurement technique to assess the magnitude of the five most prevalent noise types found in free-running oscillators, intended for use in true random number generation. The noise types under study range from white thermal- to flicker- and random walk noise, acting either on the oscillator phase or frequency. A time domain study establishes an analytical connection between the oscillator excess phase variance and the accumulation time length. A variance model that characterizes the phase measurement method is developed, taking into account that one noise type will dominate over all other handled noise types within a specific measurement interval. Additionally, this model considers the effects of both test setup induced variance and quantization noise. The measurement method utilizes a differential approach based on Delay Chains (DCs) and is implemented using a 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. A time resolution less than 100 ps could be achieved, effectively lowering the quantization noise floor and allowing to examine jitter accumulation at a time scale down to 30 ns. Measurement results show that typical CMOS ring oscillators are predominantly affected by flicker noise, creating long-term dependencies between the generated period jitter. This observation might in turn invalidate the popular assumption of mutual independence between successive oscillator periods, made in many true random number generator stochastic models. A noise corner is observed at the lower end of the measured accumulation time interval, below which thermal noise becomes dominant over flicker noise, and consecutive period jitter can be considered mutually independent again.

Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.

We have designed single-bit comparators and multi-bit flash analog-to-digital converters (ADCs) using three flavors of periodic comparators; one flavor uses a differential “quasi-one-junction” SQUID (DQOS) comparator, the second use a differential SQUID wheel comparator (DSW) and the third uses a symmetric differential SQUID wheel comparator (SDSW) with time-interleaved clocks. We have also developed a new performance analysis scheme that enables full reconstruction of input signal using a single-bit comparator. The signal is reconstructed based on multiple beat frequency measurements that track the position of the comparator thresholds in response to a dc offset to the input signal. In addition, to eliminate the frequency dependent distortions resulting from impedance mismatches over wide bandwidths, the signal and clock distribution network have been optimized using EM simulations. For distributing the clock signal to the multi-bit comparators, a 50 Ω coplanar transmission line has been designed. Test results for a 1-bit DSW comparator demonstrates a performance of 4.5 bits of resolution in Gray code for a beat frequency test using a 20 GHz input signal and 5.3 bits for 10 GHz input. 4 and 8-bit versions of the flash ADC with a DQOS comparator and a 3-bit time-interleaved ADC using the SDSW comparator have also been designed. The DQOS ADC has been tested up to 25 GHz input signal frequency with performance of 4.3 bits of resolution in Gray code for 19.7 GHz input signal. The time-interleaved ADC performance is 4.3 bits for a 15 GHz beat frequency test with an effective sampling rate of 30 GHz.

This paper presents an on-chip 13 bits 10 M/S Analog to Digital Converter (ADC) specifically designed for infrared bolometric image sensor. Bolometric infrared sensors are MEMs based thermal sensors, which covers a large spectrum of infrared applications, ranging from night vision to predictive industrial maintenance and medical imaging. With the current move towards submicron technologies, the demand for more integrated, smarter sensors and microsystems has dramatically increased. This trend has strengthened the need of on-chip ADC as the interface between the analog core and the digital processing electronic. However designing an on-chip ADC dedicated to focal plane array raises many questions about its architecture and its performance requirements. To take into account those specific needs, a high level model has been developed prior to the actual design. In this paper, we present the trade-offs of ADC design linked to infrared key performance parameters and bolometric technology detection method. The original development scheme, based on system level modeling, is also discussed. Finally we present the actual design and the measured performances.

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

Implementation of photonic analog-to-digital convertor (ADC) using an optimal way of information parallelizing at the level of circuit solutions can significantly improve the performance of the total system (signal source - ADC - computing device). Traditional approach for fast photonic ADC uses processing every time-neighbor sample of input signal by its own channel. For the input signals with limited bandwidth, another approach can be used, in which every input signal spectral interval is processed by its own channel, and the width of the spectral interval is adjusted with the performance of an electronic ADC used for digitizing. In many cases, output signals of electronic ADCs are sufficient for obtaining necessary information from the input signal without joint processing of the output signals of all channels; otherwise, outputs of all channels can be Fourier-processed and concatenated to get complete spectrum of a wideband microwave input signal. For realization of this scheme, a mode locked stable laser together with an amplitude modulator and two combs of narrow band optical filters can be used. Alternatively, a mode locked laser can be replaced with a continuous wave (CW) laser together with a number of optical modulators. Performance capabilities for signal ADC using spectral intervals are estimated. Parameters for optimal system operation are derived. It is shown that, for modern optical elements, 8-10 effective bits can be achieved in the digitized signal.

This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step.

This paper investigates the multi-user full-duplex massive multiple-input multiple-output (MIMO) amplify-and-forward (AF) relaying system with low-resolution analog-to-digital converts (ADCs), where the zero-forcing transmitting/ zero-forcing receiving (ZFT/ ZFR) precoding scheme is employed. By modeling the loop-interference and quantization noise as additive noise, we perform the analysis of the achievable spectral efficiency (SE) that is given with closed-form expressions. Then, we present the asymptotic analyses under three different power-scaling scenarios. Comparison analysis shows that, with different power-scaling schemes, the system has different ability to restrict the effect of loop interference and low-resolution ADCs. Specially, the impact of loop interference and quantizer errors on achievable SE is restricted effectively only under the power-scaling scenario where the relay's transmit power is scaled down with the number of transmit antennas at relay. At the same time, the effect of loop interference can be also restricted under the case where both the transmit powers at sources and relay are scaled down with the relay's antenna number. The results can be used to guide the design of massive MIMO relaying systems so that the hardware cost and energy consume can be deduced significantly.

Shot and Johnson noises are often incorrectly thought of as two independent noise sources. This incorrect picture has affected the evaluation of detectivities in interband cascade infrared photodetectors (ICIPs). In this work, a unified picture of shot and Johnson noises is developed for ICIPs based on a fundamental framework to understand the origin of Johnson noise and clarify the possible confusion between Johnson and shot noises. General, yet concise expressions are derived to evaluate the current noise power spectral density and detectivity for ICIPs even with complicated structures. Also, simple expressions for the signal current due to absorption of photons and the corresponding photon noise are derived, consistent with the previous results derived from alternative methods. Furthermore, a formula is derived to correctly evaluate the detectivity for conventional photodetectors under a reverse bias. The derived formulas with discussion are expected to improve the understanding of noises in ICIPs and other types of photodetectors and help us to appropriately evaluate their detectivities.

Digital pulsed ultra wideband (UWB) receivers offer numerous advantages compared to architectures based on analogue correlation, but present unique implementation challenges. The specification of the Analogue-to-Digital Converter (ADC) resolution constitutes one of the most critical activities in the design of digital UWB receivers. Moreover, multi-bit ADCs must be associated with an Automatic Gain Control block which avoids the sub-optimal regimes of the ADC dominated by quantisation or saturation noise. This paper shows how to determine the ADC resolution requirements and the optimal Automatic Gain Control (AGC) settings for the general class of digital receivers. We conclude that 3 bits provide sufficient resolution on condition that the AGC scales the input signal at a reference root mean squared (RMS) level of half the ADC saturation voltage.