Analog to Digital Conversion

With the change in advanced technology and the need for electronic equipments, the development of electronic instruments stimulate more efforts for more innovative ideas and better performance of design. In real world physical values, such as pressure, humidity, temperature and voice can be measured as analog (continuous) signals. However, to process these analog signals by electronic digital equipments, we need to convert these analog signals into digital or discreet signals or binary. In this paper, there are many types of Analog-to-Digital Converters (ADCs) which can be classified according to the applications and concept on which they were designed. ADCs including, Direct conversion ADC (Flash), successive approximation ADC, integrating ADC, Pipeline ADC. In some cases, many comparators are used to reduce the complexity, power and improve the linearity which are also explained in this paper.

Optical communication systems, which operate at very high rates, are limited by the sampling rate bottleneck. The optical wideband regime exceeds analog to digital converters (ADCs) front-end bandwidth. Multi-channel sampling approaches, such as multicoset or interleaved ADCs, have been proposed tho sample the wideband signal using several channels. Each channel samples below the Nyquist rate such that the overall sampling rate is preserved. However, this scheme suffers from two practical limitations that make its implementation difficult. First, the inherent anti-aliasing filter of the samplers distorts the wideband signal. Second, it requires accurate time shifts on the order of the signal's Nyquist rate, which are challenging to maintain. In this work, we propose an alternative multi-channel sampling scheme, based on analog RF demodulation, where each channel aliases the spectrum using a periodic mixing function before integration and sampling. We show that intentionally using the inherent ADC filter to perform integration turns it to an advantage by increasing the signal to noise ratio (SNR). We demonstrate both theoretically and through numerical experiments that our system outperforms multicoset in terms of signal recovery and symbol estimation in the presence of both thermal and quantization noise.

Programmable logic controller (PLC) is connected with analog and digital input and output modules to process physical variables which are to be maintained at the desired values. Each module has a processor to process analog or digital signals. This paper has designed analog input module (AIM) using field programmable gate array (FPGA). It has used a digital to analog converter (DAC), comparator and FPGA for a single channel analog to digital converter (ADC). It becomes an analog input module (AIM) when a DAC and comparator are added to FPGA for every addition of a channel. Conversion time of a processor based AIM is n*tc where ‘n’, ‘tc’ are the number of channels and conversion time of ADC respectively. Conversion time of ‘n’ channel FPGA based AIM is ‘tc’ as all the analog signals are processed concurrently. The design was experimented using Multisim software and the conversion time of eight channels ADC was identified 0.13 ms.KeywordsProgrammable logic controllerADCMicroprocessorFPGA

Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.

Chapter 6 - Analogue to Digital and Digital to Analogue Conversion

Analog signals are converted into digital signals for digital signal processing. Analog-to-Digital Converter (ADC) is used for the conversion process. When required, Digital-to-Analog Converter (DAC) is used for reconverting the processed digital signals into analog signals. Sample-Hold amplifier, Anti-aliasing filter, Reconstruction filter and Operational amplifier (Op-amp) are the analog components that are generally used in signal conversion circuits. The operation of the analog components is presented. Four ADC architectures, namely, Flash ADC, Dual slope ADC, Successive approximation ADC and Sigma-Delta ADC, are explained. Two DAC architectures, namely, Binary-weighted input DAC and R-2R Ladder DAC, are explained.

Data converters bridge the gap between the physical world of analog signals and the abstract world of mathematics and representational data. Digital-toanalog converters (DACs) convert a sequence of digital numbers into an analog signal, and analog-to-digital converters (ADCs) convert an analog signal into a sequence of digital numbers. In this book, the analog signals we will be discussing most will be derived from imagery collected through detecting elements. Data converters have been around longer than you might expect. Walt Kester of Analog Devices published the Analog-Digital Conversion Handbook online in 2004 and included a wonderfully extensive history of data conversion that extended back to the 18th century. Kester outlines an extremely early DAC developed in the early 18th century in the Ottoman Empire. This early data converter was an 8-bit binary-weighted hydraulic DAC used to control water distribution. Nozzle size was weighted for water flow in a binary fashion, allowing controllers to change the flow with 28 or 256 individual settings using only eight nozzles. In this case, the input is coming directly from human operators, and the output is water current, making this also the first documented current DAC with flowing water molecules instead of electrons. Analog-to-digital converters were developed much later. In a 1921 patent, Rainey disclosed what might be the first electro-mechanical ADC for his facsimile system. This converter utilized a light beam, photocells, a galvanometer, and 32 relays to reproduce data printed on a transparency into an "m-hot out of 32" digital word. This is a 5-bit thermometric output similar to a typical 5-bit flash ADC, which will be discussed in Chapter 4. It might be fascinating to image sensor professionals that this ADC utilized photonic components almost 100 years ago. In 1937, Reeves, at the International Telephone and Telegraph Corporation in Paris, is credited with the first all-electronic DAC and ADC design with his pulse code modulation patents. Electronic converters quickly became necessary components in every electronic component interfacing to real-world signals. Jumping forward a little more than 50 years to the late 1980s brings us to the beginning of the era of the low-cost, high-volume image sensor. Eric Fossum, the father of the modern CMOS active pixel sensor, published a very early report of image processing that included ADCs integrated on a focal plane array.2 In Smart CMOS Image Sensors and Applications, Jun Ohta suggests that it is possible that Eklund, Svensson, and Astrom published the first column-level ADC on an image-sensing chip in 1995. So began the revolution in digital imaging systems-on-chip, which has led to the prevalence of high-quality, low-cost image sensors in modern electronics.

System control and the collection of analog signals are fundamental tasks in many embedded computer systems such as are found in automotive, communication, and sensor network domains. Often latency is critical and FPGAs are an attractive alternative. Traditionally, external ADC (analog to digital converter) chips have been used for analog to digital signal conversion and transfer of the digital signals to the FPGA(s). In large-scale quantum system experiments, the implementation of this classic control infrastructure is a challenge. In particular, the FPGA-based control system must work in a liquid helium environment at about 4°K. To improve the system's reliability, we need to integrate multiple lanes of soft core ADC directly into the FPGA. In this paper we propose a method of building high-speed ADCs with time to digital converters (TDCs). The experimental results show that the ADCs can achieve a sampling rate of 100Msa/s with a 6-bit resolution for signals ranging from 0 to 3 V. In our design the ADC uses primarily the ISERDES logic of a Xilinx FPGA plus a small number of CLBs. Our design can integrate 24 lanes of soft-core ADCs into a Xilinx XC7A100t-2csg324 FPGA.

Synthetic instruments apply the flexibility and computational capabilities of a digital signal-processing platform to synthesize a wide variety of synthetic instruments. The emphasis presented in traditional descriptions of a synthetic instrument is the architecture and the capabilities of the digital signal processing (DSP) platform and the user interfaces to the same. In this paper we highlight and discuss considerations of the signal conditioning and signal collection tasks. The focal point of the signal collection process is the analog-to-digital converter (ADC), the element that defines the precision and the bandwidth of the sampled data representation of the signal processed by the DSP platform. Analog signal conditioning prior to the ADC performs the task of limiting the input signal bandwidth and possible translation of the spectral band center. Digital signal conditioning following the ADC continues to perform the same tasks by further limiting the bandwidth of the digitized input signal as well as performing spectral translation with appropriate sample rate changes. In addition, the post conversion process can correct gain, phase, and time delay imbalances between input signal paths as well as gain and phase distortion encountered in the analog signal path. We identify and address performance constraints of existing ADCs and present a number of signal processing-based options to enhance and extend the operating regimes of the analog signal conditioning and the ADC conversion process.

In practical compressive sensing (CS) communication system, Analog to Digital Converter (ADC) is a necessary component to convert analog signals into digital ones. However, nonlinear distortion in ADC is unavoidable and definitely affects the reception accuracy. Though recent works have studied various methods to combat the negative effect of ADC nonlinear distortion, few of them discuss the solution in communication system with CS. This paper studies the CS recovery method when compressive measurements suffer from ADC nonlinear distortion. A double-sparsity model is first formulated, where the original signal and the ADC nonlinear distortion are both sparse. Then, for the type of clipping ADC, we propose a corresponding algorithm based on the Alternating Direction Method of Multipliers (ADMM) strategy to solve the double-sparsity (DS) problem, named as DS-ADMM. For the type of self-reset (SR) ADC, we explore its essence of rounding operation to design an integer constraint based feedback updating (ICFU) strategy, and accordingly propose the DS-ADMM-ICFU recovery algorithm. Experiment results show that the DS-ADMM algorithm for the double-sparsity problem improves the recovery performance compared with the existing counterpart, and DS-ADMM-ICFU for SR ADC exhibits preferable advantage in typical communication systems.

The ADCs characteristics that make up the MC don't always correspond to the specified requirements for accuracy and noise level. The thesis paper describes a new type of ADC with phase-locked loop (ADC with PLL). Currently, the development of a number of electronic devices is conducted jointly with the use of various microcontrollers (MK), which includes analog-digital converters (ADCs). A new type of ADC allows improve these characteristics, having a relatively simple circuit design implementation. Using the PLL loop, the input level voltage (analog signal) is converted into a digital frequency signal of a variable pulse ratio. The converted signal (analog voltage) is applied to one of the low-pass filter (LPF) inputs included in the PLL, thereby removing the circuit from equilibrium, changing the pulse ratio of the output signal.

Present days witnessed extensive use of Analog to Digital Converters (ADC) in different fields of applications, as an interface between the analog world and the digital world. However, in most cases, external ADCs are employed to meet the purpose. This eventually makes the system bulky, power-consuming, complex, and costly. Implementation of reconfigurable ADC programmed inside Field-Programmable Gate Array (FPGA) could reduce the system cost and power consumption substantially. Furthermore, this will make the system simple as it does not require any external circuitry for the conversion of analog input data into digital form for processing. Thus, in this paper, a multichannel reconfigurable ADC is designed, with an additional feature of time multiplexing for efficient data acquisition. The design is being implemented using 100MHz FPGA clock frequency thus can achieve a sampling rate of 100 MS/s with a resolution of 10bit for 0-2.5V signal range. The FPGA resource utilization for the complete ADC model consists of 341 FFs and 265 LUTs, with total on-chip power consumption of 14.428 W. The proposed system can also be implemented for different analog signal from transducers, depending upon the demand and requirement of sensing parameters the data collection time can be varied for transducer to transducer.

11 - Analogue and digital conversions

Widely used in telecom, television, music players, and controllers, a digital-to-analog converter (DAC) is a device that converts a digital signal into an analog signal. As integrated circuits (ICs) technologies develop, the modulation process has shifted from analog circuits to digital circuits, and the signal has been converted from a digital signal field to an analog signal field. Generally, the design of digital circuits is simpler than that of analog circuits, so the transferring can decline the requirement and difficulty of the system design. How the final DAC performs on the printed circuit board (PCB) directly affects the system's specifications. Therefore, verifying the final parameters of the DAC becomes an important task for the whole test. The DAC chip static parameters DNLity (DNL) and integral nonlinearity (INL) require measuring all points to get the calculated results. It will cost a long time if reading and recording are done by humans. This paper presents a fast and effective method to measure the static parameters of the DAC chip. The test time depends on the measurement accuracy and data. In this paper, the chip independently developed by Beijing Smart-Chip Microelectronics Technology Co. is used as a test case for testing. The results show that the DAC testing method mentioned in this paper can greatly shorten the testing time compared with manual testing.

While various circuit noise sources, such as thermal noise, shot noise or 1∕f noise, have a physical origin, other types of noise, like quantization or roundoff noise, occur as a consequence of computational operations performed by circuits. Specifically, the digitization of bandlimited signals with analog-to-digital converters (ADCs) involves not only signal sampling in time, but also amplitude quantization. The quantization operation introduces an error, which is called quantization noise. This noise plays an important role in analyzing the performance of DSP systems and in ADC design. Bennett observed in 1948 that for a sufficiently small discretization step, quantization noise can be viewed approximately as uniformly distributed and white. In a comprehensive study of quantization noise, Widrow was able to derive precise conditions for these properties to hold. Unfortunately, because it is a function of the input signal, the quantization noise is not independent from the input, which creates undesirable artifacts in audio systems. To overcome this problem, an independent dithering noise can be added to the input signal and removed after quantization. This chapter presents a comprehensive analysis of the properties of quantization noise and dithering.