Signal conditioning and data collection in synthetic instruments [ATE systems

A signal scaling design procedure, to obtain the best noise performance for a 16-QAM discrete multi-carrier transceiver, realized on a digital signal processing (DSP) platform, is presented. The experimental results demonstrate that under the proper scaling, the bit error rate (BER) of the multi-carrier transceiver can approach a very small value. The proposed signal scaling method can be applied to other DSP based multicarrier communications systems.

Real-time implementation of a recently introduced method of measurement of distortion product otoacoustic emissions (DPOAEs) for hearing assessment is presented. Development of the real-time application begins with the discretization of the DPOAE estimation algorithm in Matlab and then programming in C for final downloading onto a digital signal processor (DSP) platform. Aside from the signal processing task involved in the estimation process, the DSP platform controls a microphone/speaker system, which generates the acoustical stimuli for presentation to the ear canal and collects the acoustical responses recorded in the ear canal. The real-time results are compared with those obtained by a continuous-time off-line model of the DPOAE estimation algorithm. The developed DPOAE measurement system offers a high degree of noise immunity and a short measurement time, both of which are of importance in clinical applications of the DPOAE signals.

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

The characterization powerline networks and investigation of communicarion performances has been the interest of several research works. Despite of its complex noise scenario and variable attenuation, narrowband powerline communication (NB-PLC) systems are key element in smart grids which provide different applications such as remote meter reading, home automation and energy management. Mainly located at the last mile communication, NB-PLC systems participate in monitoring and controlling power consumption at different level from local utilities to final customers in conjunction with wireless technology. To provide a proper communication flow over powerlines, it is primordial to get efficient designed and proven PLC systems responding to smart grids requirements. After PLC system design and development, a major task is the infield test which is a heavy task, time consuming and does not give enough information about system performance and robustness. In one hand, test and verification result are as variable as channel conditions. So, it is not obvious to get relevant information from classical infield test. In the other hand, the behavior of existing industrial PLC systems behavior cannot be accurately reproduced in simulation environment. Therefore, getting a flexible standalone platform emulating NB-PLC channel phenomena allows overcoming verification process difficulty. In literature, few research works are interested in emulating narrowband powerline.First, the idea of emulating PLC channels using a stand-alone device has started in a broadband PLC by presenting a hardware platform based on a digital signal processor (DSP) and a field programmable gate array (FPGA). Then, algorithms have been developed and optimized to reduce complexity and improve real-time performance. Regarding NB-PLC, an emulator has been proposed for indoor channels in the frequency range between 95 and 148.5 kHz using analog to digital circuit for channel transfer function and noise scenario. More flexibility and accuracy in generating the NB-PLC channel behavior has been studied and extended to support frequencies up to 500 kHz. The main challenge was the definition of time varying reference channels and tunable sophisticated noise scenarios for emulation. Both proposed NB-PLC channel emulator only takes into consideration the attenuation as predefined function and noise phenomena. The ZC detection is supposed to be ideal that it does not affect the communication performance.The objective of this research work consists in proposing a flexible DSP based NB-PLC channel emulator encompassing the channel bottlenecks interfering during communication. The channel attenuation is deduced using bottom up approach and appropriate noise scenarios are defined to meet as much as possible realistic phenomena. The effect of zero crossing variation is also taken into account. The overall parameters are optimized to be embedded on a DSP platform.

This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, challenges in large search-range ME are discussed. Then, based on the statistics analysis of the best matched block, correlations in variable block-size ME are removed on algorithm level while keeping almost the same performance as the original fast strategy. Based on this modification and data reuse technique, this paper proposes an index search method for DSP implementation, which is a good solution to balance both high coding efficiency and high coding speed on the DSP platform. In index search, ME is divided into three steps and highly parallel pipelines are designed for each step. The fully use of pipelines brings about 85% time reduction during ME. Index search can also be easily extended to achieve different range and patterns.

Modern wireless communication equipment such as outphasing power amplifiers or systems like massive-MIMO rely heavily on transmission of complex wideband modulated radio frequency signals on parallel signal paths. As these signal bandwidths increase, wireless transmitters are more susceptible to amplitude and phase distortions across frequency. We propose a novel method to quantify the complex signal distortions in each transmit path and a technique to pre-compensate the transmitter over a wide bandwidth of interest. This work has been experimentally validated with measured results on two separate RF test benches using signal bandwidths up to 100 MHz. An outphasing power amplifier bench for WCDMA at S band requiring 4 signal paths and a satellite uplink modulator using 8-PSK at Ku band requiring two signal paths were tested in the experimental validation. Further, it is also validated that this method requires only one iteration to calibrate a set of parallel RF signal paths.

In this paper, a chaotic circuit based on a memcapacitor and meminductor is constructed, and its dynamic equation is obtained. Then, the mathematical model is obtained by normalization, and the system is decomposed and summed by an Adomian decomposition method (ADM) algorithm. So as to study the dynamic behavior in detail, not only the equilibrium stability of the system is analyzed, but also the dynamic characteristics are analyzed by means of a Bifurcation diagram and Lyapunov exponents (Les). By analyzing the dynamic behavior of the system, some special phenomena, such as the coexistence of attractor and state transition, are found in the system. In the end, the circuit implementation of the system is implemented on a Digital Signal Processing (DSP) platform. According to the numerical simulation results of the system, it is found that the system has abundant dynamical characteristics.

This paper deals with the problem of synchronization of bursty offset QPSK signals in the presence of frequency offset and additive white Gaussian noise. The main tasks of the receiver are to detect a burst (a frame of data) with a low acquisition time, to estimate and cancel the frequency and phase offset (carrier recovery), perform timing recovery, matched filtering and finally recover the data such that the bit-error-rate (BER) is close to the theoretical limit. The key contribution of this paper is to develop synchronization techniques in discrete-time that perform effectively even at signal-to-noise ratio (SNR) close to 0 dB in additive white Gaussian noise (AWGN) channels. These techniques are well suited for implementation on a digital signal processing (DSP) platform.

In this paper, a discrete model of memristor is adopted and analyzed. The new discrete maps are built by introducing this discrete memristor model into a two-dimensional discrete map. Interestingly, introducing this discrete memristor model from different locations can lead to two new chaotic map models. The dynamical behaviors of the two maps are studied by means of bifurcation diagrams, phase diagrams and Lyapunov exponential spectra (LEs). The simulation results show that both chaotic systems have rich dynamical behaviors. In addition, they are experimentally found to have multi-stable properties, where the M-XM map has infinite attractors coexistence. Finally, we complete the hardware implementation of the two maps based on Digital Signal Processing (DSP) platform for the application of discrete chaotic systems.

Implementation of photonic analog-to-digital convertor (ADC) using an optimal way of information parallelizing at the level of circuit solutions can significantly improve the performance of the total system (signal source - ADC - computing device). Traditional approach for fast photonic ADC uses processing every time-neighbor sample of input signal by its own channel. For the input signals with limited bandwidth, another approach can be used, in which every input signal spectral interval is processed by its own channel, and the width of the spectral interval is adjusted with the performance of an electronic ADC used for digitizing. In many cases, output signals of electronic ADCs are sufficient for obtaining necessary information from the input signal without joint processing of the output signals of all channels; otherwise, outputs of all channels can be Fourier-processed and concatenated to get complete spectrum of a wideband microwave input signal. For realization of this scheme, a mode locked stable laser together with an amplitude modulator and two combs of narrow band optical filters can be used. Alternatively, a mode locked laser can be replaced with a continuous wave (CW) laser together with a number of optical modulators. Performance capabilities for signal ADC using spectral intervals are estimated. Parameters for optimal system operation are derived. It is shown that, for modern optical elements, 8-10 effective bits can be achieved in the digitized signal.

Testing high resolution DACs: A contribution to draft standard IEEE P1658

The development of a generic platform, which can assist patients suffering from a range of motor disabilities to perform everyday tasks is described. Methodologies were established, whereby the design could be made sufficiently flexible, that it could be programmed to suit people with a wide variety and with varying severity of motor disabilities, in terms of their needs and level of functional impairment. This needed to be achieved without redesigning the system for each person. Suitable sensors were chosen to detect the residual motor function of the disabled individual, while being noninvasive and safe for use. These sensors were connected to a signal selection and conditioning circuit and an analogue-to-digital converter (ADC). This served as an interface between the hardware and a stand-alone software application, developed to provide all the customisability and functionality for the system. The software application allowed the user to customise the digital signal processing of the various input signals, as well as allowing a user to calibrate the level at which the input from a particular sensor, triggered an output response. This helped ensure that only voluntary actions resulted in an output response. The software also facilitated the user customising the output function required. The proof-of-concept was tested by setting up the system to allow the user to operate a computer. By having volunteers with disabilities test the system, it was determined that the assistive platform was, in general, capable of satisfying various users’ diverse requirements.

This paper presents an approach for the mismatch pulse compression implementation in spread spectrum radars with binary phase intra-pulse modulated pulses. Design and verification of the matched and mismatched filter for signals coded by Barker and M sequences are accomplished on a digital radar signal synthesis and processing platform based on direct digital synthesis (DDS) and field programmable gates array (FPGA) technology. Coefficients of mismatched filters are obtained by DIRLS algorithm with 16-bit resolution. The compressors are verified with sequences lengths of 13 and 31, and bandwidth of 3.3 MHz.