Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range

In recent years, the variable block size (VBS) motion estimation technique has been widely employed to improve the performance of the block matching algorithm (BMA). In VBS, the block size is varied according to the type of motion. The VBS is known to be very efficient for areas containing complex motions. But, it requires a large amount of computation. The computation required is 2 or 5 times compared with the full search BMA. In this paper, a new VBS motion estimation algorithm, called the classified variable block size (CVBS), is proposed to overcome this problem. The algorithm classifies the input blocks into 3 categories: the background, the shade-motion, and the edge-motion. According the characteristics of the classified blocks, various motion estimation techniques are then used to improve the coding performance. The performance of VBS and CVBS under the coding efficiency is investigated. It is shown that the CVBS algorithm requires about 1/6 to 1/10 computations needed by the conventional VBS algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High external memory bandwidth requirement is one major challenge for efficient hardware motion estimation (ME) implementation. Large double-buffered on-chip search window (SW) buffer is usually employed to increase the throughput. In this paper, we focus on SW buffer structure optimization in a systematic viewpoint. An efficient buffer share mechanism is proposed to minimize the memory consumption, simultaneously alleviate the external memory access bandwidth. Moreover, variable block size ME (VBSME) and large SW in high definition (HD) video encoder are both supported with good trade off among throughput, data regularity, and rate distortion performance. The simplified algorithm can achieve nearly 50% SW buffer saving with less than 0.15dB PSNR degradation at the worst case compared with full search VBSME.

The key to high performance in image sequence coding lies in an efficient reduction of the temporal redundancies. For this purpose, motion estimation and compensation techniques have been successfully applied. This paper studies motion estimation algorithms in the context of first generation coding techniques commonly used in digital TV. In this framework, estimating the motion in the scene is not an intrinsic goal. Motion estimation should indeed provide good temporal prediction and simultaneously require low overhead information. More specifically the aim is to minimize globally the bandwidth corresponding to both the prediction error information and the motion parameters. This paper first clarifies the notion of motion, reviews classical motion estimation techniques, and outlines new perspectives. Block matching techniques are shown to be the most appropriate in the framework of first generation coding. To overcome the drawbacks characteristic of most block matching techniques, this paper proposes a new locally adaptive multigrid block matching motion estimation technique. This algorithm has been designed taking into account the above aims. It leads to a robust motion field estimation precise prediction along moving edges and a decreased amount of side information in uniform areas. Furthermore, the algorithm controls the accuracy of the motion estimation procedure in order to optimally balance the amount of information corresponding to the prediction error and to the motion parameters. Experimental results show that the technique results in greatly enhanced visual quality and significant saving in terms of bit rate when compared to classical block matching techniques. >

A signal scaling design procedure, to obtain the best noise performance for a 16-QAM discrete multi-carrier transceiver, realized on a digital signal processing (DSP) platform, is presented. The experimental results demonstrate that under the proper scaling, the bit error rate (BER) of the multi-carrier transceiver can approach a very small value. The proposed signal scaling method can be applied to other DSP based multicarrier communications systems.

Synthetic instruments apply the flexibility and computational capabilities of a digital signal-processing platform to synthesize a wide variety of synthetic instruments. The emphasis presented in traditional descriptions of a synthetic instrument is the architecture and the capabilities of the digital signal processing (DSP) platform and the user interfaces to the same. In this paper we highlight and discuss considerations of the signal conditioning and signal collection tasks. The focal point of the signal collection process is the analog-to-digital converter (ADC), the element that defines the precision and the bandwidth of the sampled data representation of the signal processed by the DSP platform. Analog signal conditioning prior to the ADC performs the task of limiting the input signal bandwidth and possible translation of the spectral band center. Digital signal conditioning following the ADC continues to perform the same tasks by further limiting the bandwidth of the digitized input signal as well as performing spectral translation with appropriate sample rate changes. In addition, the post conversion process can correct gain, phase, and time delay imbalances between input signal paths as well as gain and phase distortion encountered in the analog signal path. We identify and address performance constraints of existing ADCs and present a number of signal processing-based options to enhance and extend the operating regimes of the analog signal conditioning and the ADC conversion process.

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

Fast motion estimation and Inter-mode decision for H.264/MPEG-4 AVC encoding

Although variable block-size motion estimation provides significant video quality and coding efficiency improvement, it requires much higher computational complexity compared with fixed block size motion estimation. The reason is that the current motion estimation algorithms are mainly designed for fixed block size. Current variable block-size motion estimation implementation simply applies these existing motion estimation algorithms independently for different block sizes to find the best block size and the corresponding motion vector. Substantial computation is wasted because distortion data reuse among motion searches of different block sizes is not considered. In this paper, a motion estimation algorithm intrinsically designed for variable block-size video coding is presented. The proposed multiple block-size search (MBSS) algorithm unifies the motion searches for different block sizes into a single searching process instead of independently performing the search for each block size. In this unified search, the suboptimal motion vectors for different block sizes are used to determine the next search steps. Its prediction quality is comparable with that obtained by performing motion search for different block sizes independently while the computational load is substantially reduced. Experimental results show that the prediction quality of MBSS is similar to full search.

This paper proposes a new solution to improve the quality of depth map in 2D+depth map of 3D video coding. The proposed method based on H.264 variable block size motion estimation for 2D video coding in 3D video. As in the 2D video coding flow, motion estimation is also applied to depth map coding. However, the result of the predicted depth map is not precise enough only through 2D motion estimation. Therefore, a new idea grows, that is 3D motion estimation for 2D and depth video. The third dimensional search is necessary for depth information. The proposed 3D motion estimation raises the quality and the precision of the depth map after prediction, and reduces the coding bitrate. From the simulation results, the high accuracy depth map improves the effect of the 3D video viewing exported by the Depth image based rendering (DIBR) system.

Early SKIP mode decision for MVC using inter-view correlation

In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16×16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.

Motion estimation using multiple reference frames is widely used as the basis for recent video coding standards (eg. H.264/AVC) to achieve increased coding efficiency. However, this increases the complexity of the encoding process. In this paper, a new technique for efficient motion estimation is proposed. A combination of multiple reference frame selection and image residue-based mode selection is used to improve motion estimation time. By dynamic selection of an initial reference frame in advance, the number of reference frames to be considered is reduced. In addition, from examination of the residue between the current block and reconstructed blocks in preceding frames, variable block size mode decisions are made. Modified initial motion vector estimation and early stop condition detection are also adopted to speed up the motion estimation procedure. Experimental results compare the performance of the proposed algorithm with a state of the art motion estimation algorithm and demonstrate significantly reduced motion estimation time while maintaining PSNR performance.

In H.264 advanced video coding (AVC), variable block size motion estimation plays an important role in compression of interframes. In this paper, we propose a fast inter prediction algorithm based on hierarchical homogeneous detection and cost analysis to select the best mode effectively. For each macroblock, we first detect that whether the macroblock is spatial homogeneous or not. For the non spatial homogeneous macroblock, we then perform the 16times16 motion estimation and examine if the 16times16 block is temporal homogeneous or not. Once the homogeneous macroblock is detected in the above process, the best mode will be chosen as 16times16 mode. For the non-homogeneous macroblock, we then execute 8times8 motion estimation and analyze the cost of 8times8 mode and 16times16 mode for deciding the best inter mode should be 16times16 mode or any other mode. The process for searching the best 8times8 block subtype is similar to the process for macroblocks. Finally, the best inter mode is decided by selecting the inter mode with least cost from the candidate modes. Experimental results show that our proposed algorithm can save about 32~54% computation time without introducing any noticeable performance degradation

A merging procedure joining search pattern and variable block size motion estimation for H.264/AVC is proposed in this paper. The principal purpose of the proposed methods is the reduction of the computational complexity for block matching module. In fact, there are numerous contributions in the literature aiming the reduction of the computational cost needed for motion estimation. The best solution from a qualitative point of view is the full search that considers every possible detail. The computational effort required is enormous and this makes motion estimation by far the most important computational bottleneck in video coding systems. Our approach invests and exploits the center-biased characteristics of the real world video sequences, aiming to achieve an acceptable image quality while independently targeting the reduction of the computational complexity. The simulations results demonstrated that the proposal performs well.