Design and Implementation of Sigma Delta Modulators (ΣΔM) for Class D Audio Amplifiers using Differential Pairs

The purpose of this paper is to modeling and computer simulation of optimized GUI-based system-level design of Sigma Delta Modulator (SDM) based analog-to-digital converter (ADC) in which a top-down approach of designing is mainly focused to improve the resolution of single-loop continuos-time sigma delta because system-level simulation is an important part of system design and can help to estimate power consumption and noise analysis accurately. The presented GUI for the noise calculation and transistor level circuit design and output simulation of Sigma delta modulator based ADC along with its various components like operational trans-conductance amplifier (OTA), Analog-to-Digital converter (ADC), Digital-to-Analog converter is well taken care here to achieve optimized performance. The simulation results show performance of modulator in transistor level and circuit design that are compatible with each other where output was generated successfully in transistor level circuit design along with its waveforms.GUI (Graphical User Interface) allows us to calculate the noise parameters and power consumption parameters. The resolution of modulator is mainly affected by the noise parameters as thermal noise, clock jitter noise, and slew rate of amplifiers, quantization noise, which leads for consumption of power. The modulators offers phase margin 92.84°, gain bandwidth product of 31.89 kHz, Unity gain bandwidth of 1.2295 kHz, That consuming power of 1.430 mW. Even with the high order of modulator, the complexity increases and the device get bulky. When the technology reduces there is possibility for improvement and getting good results. Thus, the CT ∑∆ modulator architecture is well designed and implemented using Tanner EDA tool and with the help of GUI the noise and power consumption parameters have been analyzed.

Sigma-delta ACD has two main parts: analog modulator and digital filter, the performance of modulator determines the performance of sigma-delta ADC, so the design of modulator is very important. The paper introduces the principle of sigma-delta AD modulator with high accuracy and the applied over sampling technique, noise shaping technique and multi-bit quantizer technique. Determining the design scheme of modulator—three bits three orders CIFF(Cascade of integrators, feed forward form) structure, and it makes the behavior level verification for this scheme by Simulink tool in MATLAB. The simulation result shows that multi-bit quantizer modulator can get very high SNR, and based on this result it designs every part of the modulator circuit.

This paper is devoted to the discussion of a new kind of sigma-delta modulator as signal expression, by which the higher-bit input signal can be represented as a lower-bit digital signal. The quantized noise shaping and noise frequency spectrum are discussed and compared with the conventional sigma-delta modulator. The theoretic analysis shows that the new modulator is stable. A kind of DDC based on this modulator is designed and simulated.

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM, which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Multistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed, which balances the requirements of tone-free and maximum operation frequency.

This paper presents an elaborate plan and optimization method for designing and implementing low-order band pass digital sigma-delta modulator with high order output dynamic range (DR). The noise suppression in the pass band region of the modulator and high order output DR would be achieved by designing and optimizing the Noise Transfer Function (NTF) based on over sampling ratio (OSR) and desired modulator operational frequency and designing the Signal Transfer Function (STF) by the mean which the optimum gain in desired frequency would be acquired. Designed and optimized modulator has been implemented completely on digital circuits and it would be shown that the first order designed modulator has the output dynamic range of 90dB which corresponds to 15 bits data conversion. Results from various simulations illustrate both the stability and high performance of the design and flexibility of the overall structure.

This paper describes the design and experimental characterization of a 130-nm CMOS cascade SigmaDelta modulator intended for multi-standard wireless telecom systems. Both architectural-and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Blue-tooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8 dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5 mW, of which 11.0/10.5/24.8 are due to the analog part of the circuit+1.

This paper presents a mixed equation-based and simulation-based design methodology for continuous-time sigma-delta modulators from high level specifications down to layout. The calculation and scaling of the sigma-delta coefficients as well as circuit sizing and layout generation are implemented in the same analog design environment CAIRO+. The design of a complete third order current-mode continuous-time sigma-delta modulator is taken as an example to show the effectiveness of the proposed design methodology.

The design for high speed /spl Sigma//spl Delta/ modulator is discussed, Comparison between current-mode and switched-capacitor /spl Sigma//spl Delta/ modulator performance is given. Fast-speed CMOS amplifier and comparator are designed to implement the circuit. In 1.08 /spl mu/m CMOS process current-mode /spl Sigma//spl Delta/ modulator achieves 100 MHz sampling rate.

An electromechanical sigma-delta modulator (EMSDM) is a good choice for inertial sensors to achieve high performance. However, there are few systematic methodologies to design it, due to a lack of degrees-of-freedom for implementing an arbitrary noise transfer function (NTF) in many EMSDM architectures. Previous work presented an unconstrained architecture to systematically design the EMSDM, enabling arbitrary placement of NTF poles, but NTF zeros were still constrained. Yet, the placement of the NTF zeros significantly impacts on the EMSDM noise-shaping performance. This paper proposes a nearing-free constrained architecture to address this issue. Based on this architecture, a simplified systematic design methodology for the EMSDM is demonstrated by using a capacitive MEMS accelerometer as an example. Simulation and experimental results validate that the novel architecture EMSDM accelerometer exhibits superior noise performance compared to the previously proposed unconstrained architecture EMSDM accelerometer. Furthermore, the advantages and disadvantages of the novel architecture are discussed.

Sigma delta and robust sliding mode controllers for high fidelity PWM audio power amplifiers are designed and evaluated. The used theoretical approach allows, for both controllers, an integrated design of the control, modulator and semiconductor drive electronics. The sliding mode controller shows much better tracking performance with faster dynamics, no steady-state errors, flatter passband response, due to the intrinsic Just In Time (JIT) switching operation, step response without overshoot due to the third-order Bessel control polynomial, and short circuit proof operation. Test results confirm that the sliding mode controller exceeds the performance of existing sigma delta controllers. Furthermore, the proposed sliding mode approach provides a new, nonlinear theoretical frame for solving the control problem of PWM audio power amplifiers with output filters.

The analysis, design, simulation and evaluation of 2 nd , 3 rd and 4 th order ΣΔ modulator and loop filter respectively are discussed, in this paper, to show their impact on the performance of fractional-N PLL-FS for GSM system. All simulation results show that the system is stable. The resulting settling time, spurious level and phase noise at 20 MHz offset frequency of this synthesizer for 2 nd , 3 rd and 4 th order ΣΔ modulator and loop filter respectively are 2.92 µs, -35 dBc, -164 dBc/Hz, 3.28 µs, -64 dBc, -186 dBc/Hz, 3.38 µs, -79 dBc and -190 dBc/Hz for 2 nd , 3 rd and 4 th order respectively. These results show the improvement in the spurious level and phase noise by -19 dBc, -31 dBc/Hz for 3 rd order system and -34 dBc, -35 dBc/Hz for 4 th order system respectively compared to the published work. CppSim program and Matlab (R2007a) are used for the simulation of ΣΔ fractional-N PLL-FS.

In this paper, the design of a continuous-time baseband sigma-delta (/spl Sigma//spl Delta/) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF /spl Sigma//spl Delta/ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF /spl Sigma//spl Delta/ modulator is 0.2 mm/sup 2/ in 0.35-/spl mu/m CMOS.

this paper studies a kind of hearing aid device based on Bluetooth technology and single chip microcomputer. According to the degree of hearing loss of hearing-impaired children, appropriate gain is selected to realize sound amplification, so that children with hearing impairment can hear the outside sound clearly and provide convenience for their life. This design adopts the design idea of the host and slave, the audio amplification parameters in the host are wireless transmitted to the slave through Bluetooth technology, and the audio code coding chip is given instructions. By selecting the appropriate audio signal amplification gain, the audio signal is amplified and processed, so that the hearing-impaired children can hear the external sound clearly. In this design scheme, the system hardware module design mainly includes the system control module, audio module, power module, Bluetooth communication module, etc., among which the audio module also includes the microphone input signal conditioning circuit, audio codec circuit, audio interface circuit, etc. The software platform uses the STM32F103xx firmware library provided by STMicroelectronics Company, and uses the library function provided by it and the corresponding instance to modify and debug.

A single-chip Integrated circuit of 3.3 V/1 W class-D high fidelity and high efficiency audio power amplifier is presented in this paper. The design has been done using a 3.3 V/0.25 /spl mu/m CMOS process. The maximum output power is 1 W before the amplifier saturates. The THD+N at 0.5 W output power is below 0.03% and efficiency is better than 90% thanks to the careful design of the output stage. The dynamic range is more than 100 dB suitable for high fidelity audio applications. A single-loop single-bit third order sigma-delta modulator is used to generate the PWM signal from input audio signal. The PWM signal is then filtered at the output with a second order low pass filter external to the chip to regenerate the input signal.

This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.