The design of high-speed sigma-delta modulator

In this paper, the design of a continuous-time baseband sigma-delta (/spl Sigma//spl Delta/) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF /spl Sigma//spl Delta/ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF /spl Sigma//spl Delta/ modulator is 0.2 mm/sup 2/ in 0.35-/spl mu/m CMOS.

Given an integer /spl sigma/>1, a vector (/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/), of nonnegative integers, and an undirected graph G=(V, E), an L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring of G is a function f from the vertex set V to a set of nonnegative integers, such that |f(u)-f(v)|/spl ges//spl delta//sub i/, if d(u,v)=i, for 1<i<(/spl sigma/-1), where d(u, v) is the distance (i.e., the minimum number of edges) between the vertices u and v. An optimal L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring for G is one using the smallest range /spl lambda/ of integers over all such colorings. This problem has relevant application in channel assignment for interference avoidance in wireless networks, where channels (i.e., colors) assigned to interfering stations (i.e., vertices) at distance i must be at least /spl delta//sub i/ apart, while the same channel can be reused in vertices whose distance is at least /spl sigma/. In particular, two versions of the coloring problem - L(2, 1, 1) and L(/spl delta//sub 1/, 1,..., 1) - are considered. Since these versions of the problem are NP-hard for general graphs, efficient algorithms for finding optimal colorings are provided for specific graphs modeling realistic wireless networks, including rings, bidimensional grids, and cellular grids.

Let /spl delta//sub /spl Sigma// be a measure of the relative stability of a stable dynamical system /spl Sigma/. Let /spl tau//sub A(/spl Sigma//) be a measure of the computational efficiency of a particular algorithm A which verifies the stability property of /spl Sigma/. For two representative cases of /spl Sigma/, we demonstrate the existence of a particular measure /spl delta//sub /spl Sigma// and an algorithm A such that, /spl delta//sub /spl Sigma///spl tau//sub A(/spl Sigma//)=c where c depends possibly on the dimension of the system /spl Sigma/ and parameters which are specific to the algorithm A, but independent of any other system characteristics. In particular, given /spl Sigma/ and A, one can estimate /spl delta//spl Sigma/ by measuring /spl tau//sub A(/spl Sigma//).

Using oversampled sigma-delta (/spl Sigma/-/spl Delta/) techniques a signal can be represented as a single bit binary data stream ({-1, 1}), with the quantization noise high pass filtered out of baseband. In this paper adaptive LMS digital filters are presented that directly use binary /spl Sigma/-/spl Delta/ input streams and update the PCM adaptive filter weights at the oversampled rate to realize architectures that are very suitable for mixed analog/digital VLSI implementation. Using the /spl Sigma/-/spl Delta/ adaptive architecture PCM values are multiplied by single bits, and can therefore be easily performed by a simple multiplexor. Also using the /spl Sigma/-/spl Delta/ approach, the decimation and interpolation stages required for converting from /spl Sigma/-/spl Delta/ to PCM (and vice-versa) suitable for Nyquist DSP algorithms are circumvented. The paper describes the sigma delta adaptive LMS filter architecture and presents preliminary results for adaptive echo cancellation using adaptive sigma delta and standard PCM architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In the context of a /spl Sigma//spl Delta/ analog-to-digital converter (ADC) or digital-to-analog-converter (DAC), single-bit quantization is preferred because a 1b DAC is inherently linear. A multi-bit DAC needs to be linear to avoid being the performance-limiting factor in a CB converter. Aside from this drawback, multi-bit quantization is attractive because it improves /spl Sigma//spl Delta/ modulator performance by increasing the modulator resolution or increasing the modulator bandwidth, while at the same time whitening the quantization noise and improving modulator stability. Among many dynamic-matching schemes existing today, the butterfly shuffler is effective and practical. Thus far, schemes based on the butterfly shuffler are used to whiten or to 1/sup st/-order shape mismatch errors. This paper presents a model of the structure which shows how a butterfly shuffler can be endowed with arbitrary mismatch-shaping characteristics. A 2/sup nd/-order bandpass shuffler is given as an example. A 16-element switched-capacitor (SC) DAC is designed and fabricated with a 1.2 /spl mu/m double-poly CMOS process. An 8/sup th/-order bandpass /spl Sigma//spl Delta/ modulator is implemented on a Xilinx FPGA along with the 2/sup nd/-order bandpass shuffler to drive the DAC. The system diagram is shown. The harmonic distortion is reduced by as much as 27 dB, resulting in a dynamic range of 90 dB at 125 kHz center frequency.

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allows direct sampling of the RF signal, reducing analog hardware, and makes it easier to realize completely software programmable receivers. This paper presents the circuit design of and test results from a continuous time tunable IF sampling 4/sup th/ order bandpass delta-sigma modulator implemented in InP HBT IC technology for use in a multi-mode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The 4/sup th/ order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wideband and narrowband operation. The IF is tunable from 140 MHz to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5 V power supplies, the fabricated 4/sup th/ order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal to (noise+distortion) ratio (SNDR) of 78 dB @ 1 MHz BW and 50 dB @ 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB @ 1 MHz BW and 47.7 dB @ 60 MHz BW.

We present novel oversampled implementations of adaptive LMS FIR filters using sigma delta (/spl Sigma//spl Delta/) computation strategies. Using this approach in conjunction with /spl Sigma//spl Delta/ DACs and ADCs the need for expensive decimation and interpolation stages for the /spl Sigma//spl Delta/ codec has been circumvented. Hence the complete architecture can make considerable savings in total silicon area for a mixed signal ASIC implementation. The LMS algorithm performance of the /spl Sigma//spl Delta/ approach is shown to be comparable to the traditional Nyquist rate PCM LMS algorithm.

A quadrature bandpass /spl Delta//spl Sigma/ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward "complex A/D conversion" of an image reject mixer's I and Q, outputs. Quadrature bandpass /spl Delta//spl Sigma/ modulators provide superior performance over pairs of real bandpass /spl Delta//spl Sigma/ modulators in the conversion of complex input signals, using complex filtering embedded in /spl Delta//spl Sigma/ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-/spl mu/m CMOS process is 2.4/spl times/1.8 mm/sup 2/.

We present an integrable solution for the detection of defective sensor elements using sigma-delta-(/spl Sigma//spl Delta/)-modulation and a matched filter. The sensor element is stimulated using a pseudo random binary sequence (PRBS). The sensor signal is read out and the analog output is digitized using a /spl Sigma//spl Delta/-modulator. The binary pulse density stream of the /spl Sigma//spl Delta/-modulator is the output of the sensor system and thus should ideally contain the PRBS. A matched filter has the task of detecting the pseudo random sequence in the pulse density stream and its sampled output is compared to a threshold thus making it possible to judge the functionality of the sensor element. By evaluating the magnitude of the matched filter output it is also possible to measure the sensor sensitivity. We present a discrete solution of this method, but an integrated chip using a standard 1.2 /spl mu/m CMOS process has been designed and is being fabricated.

Conventional /spl Sigma//spl Delta/ modulators suffer from idle tones. In order to alleviate the tone problem, /spl Sigma//spl Delta/ modulators with unstable filter dynamics have been proposed. In this paper we present an analysis of the saturation characteristics and tone behavior of the double loop /spl Sigma//spl Delta/ modulator with unstable filter dynamics. We begin by deriving stability boundaries for the double loop /spl Sigma//spl Delta/ modulator with unstable filter dynamics which yield bounds on maximum internal signal levels. We then show via simulations and steady state analysis that while tonal properties are improved by using unstable filter dynamics, idle tones are not completely removed. Specifically, we show that some unstable limit cycles have an attractor region in their neighborhood which results in tones in the spectrum corresponding to the fundamental or harmonics of these limit cycles.

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.

This paper presents an investigation of the performance characteristics of a pair of bandpass Sigma-Delta (/spl Sigma/-/spl Delta/) analog-to-digital (A/D) converters. One of these /spl Sigma/-/spl Delta/ A/D converters has the conventional cascade-of-integrators structure while the other has the conventional cascade-of-resonators structure. These /spl Sigma/-/spl Delta/ A/D converters are subsequently compared in terms of their achievable signal-to-quantization noise ratios for corresponding (discrete) switched-capacitor implementations. Based on this comparison, a new bandpass /spl Sigma/-/spl Delta/ A/D converter structure is proposed which possesses the best practical features of both converters. These include, complementary signal and noise transfer functions and the fact that the zeros of the noise transfer function are constrained to lie on the unit-circle.

It is well known that /spl Sigma/-/spl Delta/ A/D converters having complementary signal and noise transfer functions exhibit high signal-to-quantization-noise ratios (SQNRs) and high dynamic ranges (DRs), but that they tend to be overly sensitive to capacitor mismatches (potentially leading to unstable converter operation) in a corresponding switched-capacitor (SC) hardware implementation. Recently, a new class of /spl Sigma/-/spl Delta/ A/D converters was developed based on magnitude-squared or magnitude complementary signal and noise transfer functions to decrease the sensitivity to capacitor mismatches at the expense of slightly lower SQNRs and DRs. This paper is concerned with the development of a novel approach to the design of /spl Sigma/-/spl Delta/ A/D converters. This approach combines the transfer function complementarity (in the overall frequency band) with signal and noise transfer function magnitude complementarity (in the signal passband) to obtain a single /spl Sigma/-/spl Delta/ A/D converter with a cascade-of-resonators configuration. Consequently, the resulting A/D converters achieve not only high-stability (arising from magnitude complementarity), but also high DR and SQNR (arising from transfer function complementarity) in the SC hardware implementation. A practical application example is given to illustrate the results.

A technique for shaping component mismatch error in the real and imaginary paths of a complex (quadrature) /spl Delta//spl Sigma/ are studied and simulated. Complex bandpass /spl Delta//spl Sigma/ modulators provide improved performance over a pair of real bandpass /spl Delta//spl Sigma/ modulators of the same order in the conversion of narrow-band quadrature intermediate frequency (IF) signals. This is possible due to elimination of redundant conjugate pairs of poles and zeros in its noise and signal transfer function. Mismatches in the modulators real and imaginary paths, however, results in spectral leakage of image band interference and image band quantization noise to the passband of the converted output. Strategic pole-zero placement, as well as adaptive techniques has been studied in earlier works. The work presented here takes advantage of the inherent dual paths of the complex bandpass /spl Delta//spl Sigma/ modulator to reduce component mismatch effects using a switched capacitor error shaping technique.

One way to increase the conversion bandwidth of the Delta-Sigma (/spl Delta//spl Sigma/) A/D converter is to use parallelism. The three main types of parallel /spl Delta//spl Sigma/ A/D converter which are practical for implementation are the time-interleaved, the parallel /spl Delta//spl Sigma/ (/spl Pi//spl Delta//spl Sigma/), and the frequency band decomposition A/D converters. In this paper, it is shown that the operation of all three approaches can be explained using the same underlying theory. This common structure is then used to explore the design tradeoffs among these architectures.