Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

SummarySuccessive approximation register (SAR) analog‐to‐digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance‐ratio quantification design for the linearity test of differential top‐plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from −0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from −0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance‐ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm2. The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency.

This paper presents a self-calibrated least significant bit (LSB) extraction circuitry, which can be used with successive approximation register (SAR) analog-to-digital converters (ADCs) for resolution improvement. The proposed design uses the comparator delay information to increase the resolution by one bit without increasing the internal capacitive digital-to-analog converter resolution or the number of comparisons in one SAR cycle. The reference delay used in the LSB extraction circuitry is generated by the stochastic self-calibration loop to track variations over time. The post-layout simulations show that the proposed design increases the signal-to-noise-and-distortion ratio of the presented 9-bit 200 MS/s SAR ADC in 65 nm CMOS by 3.35 dB with insignificant degradation in power consumption, speed, and area.

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

High-speed Nuclear Quality Pulse Height Analyzer for Synchrotron-based Applications J-F. Beche, J. J. Bucher, L. Fabris, V. J. Riot Abstract--A high throughput Pulse Height Analyzer system for synchrotron-based applications requiring high resolution, high processing speed and low dead time has been developed. The system is comprised of a 120ns 12-bit nuclear quality Analog to Digital converter with a self-adaptive fast peak detector- stretcher and a custom-made fast histogramming memory module that records and processes the digitized data. The histogramming module is packaged in a VME or VXI compatible interface. Data is transferred through a fast optical link from the memory interface to a computer. A dedicated data acquisition program matches the hardware characteristics of the histogramming memory module. The data acquisition system allows for two data collection modes: “standard” data acquisition mode where the data is accumulated and read in synchronization with an external trigger and “live” data acquisition mode where the system operates as a standard Pulse Height Analyzer. The acquisition, standard or live, can be performed on several channels simultaneously. A two-channel prototype has been demonstrated at the Stanford Synchrotron Radiation Laboratory accelerator in conjunction with an X-ray Fluorescence Absorption Spectroscopy experiment. A detailed description of the entire system is given and experimental data is shown. I. S UMMARY A fast high resolution and low dead time Pulse Height Analyzer (PHA) system for Synchrotron-based applications has been developed. This module is an addition to and completes the previously designed custom electronics for XAFS applications [1, 2]. The PHA system receives analog information from a low dead time pulse processing front-end section. The low dead time PHA system is comprised of a fast high resolution Analog to Digital Converter (ADC), a fast histogramming memory and a VME or VXI compatible interface. The VME-based system consists of one complete data acquisition channel. The VXI-based PHA system addresses the problem of simultaneous data acquisition from multiple channels. Both systems were tested at the Stanford Synchrotron Radiation Laboratory in conjunction with an X- ray Fluorescence Absorption Spectroscopy experiment. The block diagram of a single acquisition channel is shown in Fig. This work was supported by the Director, Office of Energy Research, Office of Basic Energy Sciences, Chemical Science Division of the U.S. Department of Energy under Contract No. DE-AC03-76SF00098. J-F Beche, J. J. Bucher, L. Fabris and V. J. Riot are with E. O. Lawrence Berkeley National Laboratory, Berkeley, CA 94720 USA (telephone: 510- 495-2327, e-mail: JFBeche@lbl.gov). The analog input section is built around a fast self-adaptive peak detector-stretcher described in [1]. The peak detector- stretcher includes all the necessary logic to provide pileup rejection and gating functions. The stretched signal is fed to a commercial ADC chosen to maximize throughput without compromising the differential non-linearity (DNL). This ADC is an 8Msps unit, providing 14 bit of resolution with no missing code over the full temperature range, and with an intrinsic DNL of ½ LSB. In order to improve the DNL (not adequate for nuclear spectroscopy applications), only the first 12 most significant bits are used. A 6-bit sliding scale correction [3] lowers the DNL to less than 1%. Including delays, the conversion time of the ADC is 120ns. The electronic pulse-processing amplifier, in its fastest version, shapes the energy events coming from the detector with a 250ns peaking time fourth-order, pseudo-gaussian shaping function. The conversion time of the ADC does not add to the dead time associated with the pulse-shaping amplifier. Data collection is either gated by an external synchronization signal such as an accelerator beam clock or a precise clock signal to time-stamp the data collection and measure count rates. After an analog to digital conversion has taken place, the ADC board control logic sends a request to the histogramming memory module. When the histogramming memory controller acknowledges the request, it uses the ADC data to increment by one the content of the corresponding address memory location. The entire operation lasts 130ns, which is less than the dead time of the pulse- processing amplifier. Therefore, the histogramming operation does not increase the overall event-by-event processing time of the entire system. The histogramming memory module is packaged in a VME or VXI compatible interface and is built around a dual-port static random access memory. One port is dedicated to data accumulation while the second port is mapped to the VME or VXI address and data buses. The transfer to the computer is controlled by either the synchronization signal in the form of an interrupt signal sent to the VME or VXI controller, or by the computer accessing the memory at regular time intervals. The former corresponds to the “standard” acquisition mode and the latter to the “live” mode. In standard mode the content of the histogramming memory must be erased (zeroed) before collecting any new data set.

This paper is an investigation of the effects of errors in the analog-to-digital converter (ADC) of a Fourier transform infrared (FT-IR) spectrometer on the photometric accuracy of that spectrometer. The effect of ADC errors on the spectrum after Fourier transformation is calculated analytically for monochromatic, two-line, and wide square band emission spectra. Numerical modeling is used to extend the analysis to absorption spectra, and to include the effects of noise on the amplitude of absorbance bands. These analyses showed that ADC errors can generate artifacts throughout the spectrum, although the largest effects occur at sharp spectral features. Errors as large as 8% in the amplitude of absorbance bands can be produced by ADC errors of one least significant bit (LSB), in a 15-bit ADC. These results were confirmed qualitatively by measuring the net height of the oxygen vibrational band in silicon at 1107 cm −1 using four different ADC circuit boards in the same FT-IR spectrometer. At the highest signal levels, the ADCs disagreed by as much as 4%, even though their static transfer characteristics (which were measured in a separate experiment) exhibited errors of less than ±2 LSBs.

An analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookup table. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to a 12-stage prototype Pipelined ADC implemented in 65 nm CMOS technology and is able to improve measured integral nonlinearity from -5.31/1.02 least significant bit (LSB) to -0.24/0.31 LSB at a 10-bit level, an improvement of over three effective bits.

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/−0.52 least significant bit and +0.62/−0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage.

We have designed, fabricated and successfully tested digital error-correction circuits to improve the performance of superconductive flash analog-to-digital converters (ADCs). The comparators coding the most significant bits (MSBs) are the least sensitive to the input signal, and therefore have the most threshold errors due to jitter and threshold misplacement. These errors are completely eliminated by implementing an ADC architecture using two comparators per bit, and employing logic to encode bit N by looking back to the state of the (N-1) bit. In this way, all code transitions are derived from the least significant bit (LSB) comparators. The MSB comparators are used only to encode the LSB data.

This paper discusses a method to improve the resolution of an analog‐to‐digital (A‐D) converter to detect differences less than 1 LSB (least significant bit) in the input signal. Resolution is improved by superposing dither on the input signal and averaging over many measurements. The theory and experimental verification for this method are described.This analysis calculates numerically the expectation value of the result of A‐D conversion and the expectation value of the variance, with the dither superposed on the input signal. The results show that for larger amplitude of dither, the expectation value of A‐D conversion comes closer to the real value, and the expectation value of the variance becomes larger.The relation between the amplitude of dither and the improvement of resolution is calculated as a function of the number of measurements. For example, when the number of measurements is 100 and the amplitude of dither is 0.4 LSB, the resolution can be improved to 0.05 LSB.This analysis is verified experimentally by using a white noise generator as a dither source, dc voltage standard as a signal source, and a transient recorder as an A‐D converter.

Light detection and ranging (LiDAR) technology, which leverages light instead of radio waves as the source, offers superior resolution and resistance to jamming, making it a promising alternative to radio detection and ranging (RADAR) for 3D imaging and object detection. Silicon photonics-based optical phased arrays (OPAs) enable non-mechanical beam steering, overcoming the limitations of traditional rotating LiDAR systems. In OPAs, optical phase shifts are realized with the driver IC, which provides the necessary analog voltages to the optical phase shifters. This paper presents a 32-channel OPA driver IC designed to achieve high linearity and enhanced channel-to-channel uniformity. The proposed IC integrates an 8-bit digital-to-analog converter (DAC) based on an R-2R ladder, a high-gain rail-to-rail amplifier, and an I²C serial interface to support scalable multi-chip operation up to 128 channels. Key design strategies include layout optimization of resistors and MOSFETs within the driver to reduce mismatch and improve channel consistency under process variations. Fabricated in a 180 nm CMOS process, the proposed IC delivers monotonic DAC operation with a worst-case differential nonlinearity (DNL), which quantifies the deviation in step size between adjacent codes, of 0.52 least significant bits (LSB), and an integral nonlinearity (INL), which measures the deviation of the DAC transfer function from an ideal straight line, of 0.81 LSB, validating its process-robust design. Beamforming simulations using measured DAC performance demonstrate minimal performance degradation, with less than 0.2% main lobe intensity loss and negligible side lobe suppression ratio degradation. These results confirm that the proposed driver IC is suitable for robust and scalable OPA-based LiDAR systems.