High-speed nuclear quality pulse height analyzer for synchrotron-based applications

Measuring of the partial discharge (PD) parameters of the insulating systems is very important. The prompt insulating system estimation and its remaining life time give the great savings. The new, complex PD measuring methods are now developed in the world because conventional methods do not give valid information of the insulating system conditions. The goal of this paper is to show one of the new approaches in the data acquisition about PD and the measuring system performance. The measuring system consist of a few blocks: measuring bridge, multichannel analyzer (ND60), oscilloscope and personal computer (PC). The components of the measuring bridge are corresponding filters and charge calibrators. For the signal analyzer of PD we apply the ND60 (made by Nuclear Data Inc. USA). The ND60 is a multichannel pulse analyzer, including built-in charge preamplifier, amplifier, 50MHZ analog to digital converter (ADC), monitor, 2048 channel memory and serial and parallel I/O interface. ND60 realize two data acquisition modes: pulse height analysis (amplitude analysis) and multichannel scaling (time analysis). The voltage impulse of PD represents the input in the charge amplifier (the impulse integrator-signal output is proportional to the charge transfer). Analysis of signal on a time basis enables the acquisition of data (input signal) vs. arrival time. With an ability of a usage the external sweep trigger it is possible to analyze the PD as a function of phase of input voltage (power source). The PC enables the measuring system management, data acquisition from the memory of the ND60 and its processing according to the certain algorithms.

PurposeThe purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approachA low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.FindingsCompared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.Originality/valueComparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

In this paper, we present a counter based measurement circuit for in-situ characterization of analog-to-digital converter (ADC) differential non-linearity (DNL) and integral non-linearity (INL). An array of counters collects the histogram of the ADC output code for a triangular input voltage. Since the ADC operation and data transfer operation are separated in time, the DNL and INL results are immune to noise in the measurement setup. Using the proposed characterization method, we studied short-term bias temperature instability (BTI) effects in a successive-approximate-register ADC under different operating conditions.

Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount of DNL and INL is derived. The proposed algorithm is verified by the results obtained through the conventional time-domain algorithm ran under several MC simulations. The INL and DNL of the algorithms are off by merely 1%. While the proposed algorithm obtains the INL in a few seconds, the conventional algorithm takes hours to achieve the same result. Fast calculation of the yield of the ADC is possible for a given set of values for the variance of stage parameters.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

Metal-Oxide thin-film transistors (TFTs) present unique opportunities to develop robust, low-cost and transparent electronics that can mechanically endure on flexible and stretchable substrates over large area in an industry compatible technology. Analog to digital converters (ADC) are an essential part of the Internet-of-Everything, where a multitude of sensing applications are envisaged, such as temperature and pressure sensor tags on human skin. In this work, dual-gate InGaZnO TFTs (IGZO) are demonstrated to achieve a 6-bit successive approximation (SAR) C-2C ADC operated at a clock of up to 400Hz and a power dissipation of 52.2µW at a power supply of V dd =15V. The ADC achieves a differential nonlinearity (DNL) of 0.7LSB and an integral nonlinearity (INL) of 0.58 LSB using only n-type TFTs. A figure of merit (FoM) of 66.7nJ/c.s. is achieved from an ADC on flexible substrate.

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/−0.52 least significant bit and +0.62/−0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.

An ADC design with a hierarchical double correlated double sampling for a three-dimensional (3-D) stacked CMOS image sensor is presented in this paper. To realize high speed, high resolution, and high sensitivity, we have proposed a blockparallel signal processing with 3-D structure. The block-parallel analog signal processing elements which compose CMOS image sensor, correlated double sampling (CDS) with programmable gain amplifier (PGA) array, and analog-to-digital converter (ADC) array. Spatial noise is the main contributor of image distortion in CMOS image sensor. Fixed pattern noise (FPN) does not change with time, and causes fixed distortion pattern on the image, hence FPN correction is especially challenging in the high speed CMOS image sensor. In the proposed sensor system, FPN of pixel output is removed by analog CDS. The digital CDS proposed in this paper is used to eliminate FPN caused by the device variation of analog circuits. The proposed ADC was designed with 90-nm CMOS technology. The proposed ADC with digital CDS occupies a very small circuit area of 160×160μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The block-parallel ADC performance is characterized through differential nonlinearity (DNL) and integral nonlinearity (INL) measurements. The DNL is within -1.49/+1.89 LSB, and the INL is -1.92/+2.44 LSB, respectively. FPN is reduced to the range of ±1LSB by using proposed hierarchical double CDS function.

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

The paper presents a 9-bit single slope analog to digital converter (ADC) using a two-level vernier delay line (VDL) technique. The amplitude to time conversion architecture is aim to reduce the errors due to comparator delays and input offset. Results indicated that the comparator timing error has been reduced to less than 10 ps and the offset voltage is less than 1%. The time conversion part has the maximum sampling rate of 50Msps and the time resolution of 19.5ps with the differential non-linearity (DNL) within ±0.5 LSB, and the integral non-linearity (INL) within -0.22 and 0.56 LSB. The ADC has a sampling rate of 5 Msps and is realized with the CMOS 0.18um 1P6M technology.

An 8-bit, 15 kS/s programmable dual-slope (DS) Analog to Digital Converter (ADC) used in a single-chip RFID sensor nodes is presented. The ADC can be programmed to turn on and off by the RFID control unit to save power by almost 50%. Fabricated in 130 nm CMOS process, it occupies a small area of 0.06 mm2. ADC characterization is done on a stand-alone ADC that is always active, and consumes a low dynamic power of 44 µW. The measured differential non-linearity (DNL) is within +/− 0.6 LSB, effective number of bits (ENOB) is 7 bit.

This study describes the highly‐digital 4‐bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time‐to‐market and is scalable with technology. The comparators used in the ADC consist of complementary metal–oxide–semiconductor (CMOS)‐based inverter and NAND‐NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal‐to‐noise and distortion ratio, signal‐to‐noise ratio and spurious‐free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non‐linearity (DNL) of this ADC is ± 0.25 LSB and integral non‐linearity (INL) is + 0.6 LSB.

Effects of error in code transition levels on nonlinearity and effective number of bits (ENOB) of an analog to digital converter (ADC) are presented in this article. Error in code transition level is determined by deviation of code transition levels from the mean of the estimated code transition levels. Errors in estimate of differential nonlinearity (DNL), integral nonlinearity (INL) and ENOB are computed by considering error in code transition levels and computing corresponding values. In this study, 5- and 8-bit ADC transfer characteristics are simulated and arbitrary nonlinearity errors are introduced. Suitable corrections are applied in code transition levels and computation of estimate of nonlinearity with and without corrections are reported. Results have been compared with earlier published work and improvements are observed. Effects of overdrive and additive noise on ENOB for 5-bit ADC are also reported.

This paper presents a Digital-to-Analog Converter (DAC) for shuttling operations in a trapped-ion quantum computer (TIQC) measured at 4.6 K.We provide an extensive analysis and comparison of measured characteristics at room temperature (RT) versus those at cryogenic temperature (CT), particularly focusing on the DAC’s static and dynamic behavior, as well as its noise performance. By making well-conceived analytical design choices, we show that the DAC’s performance at CT can match its performance at RT. This is achieved through sufficient design margins, the selection of suitable components, and the adjustment of biasing voltages. The investigated chip features a 12 bit, resistive R-2R ladder-based DAC, which also comprises an input buffer for the DAC’s reference voltage and a simplistic SPI to read the digital control words. Implemented in Infineon’s 130nm Bipolar-CMOS-DMOS (BCD) technology, the DAC consumes 1.1mW from a 1.5V power supply at RT. Its power consumption increases to around 1.5mW at CT due to necessary biasing adjustments. The DAC’s linearity, characterized by its Differential-Non-Linearity (DNL) and Integral-Non-Linearity (INL) remains almost unchanged across temperatures, aligning with its Spurious-Free Dynamic Range (SFDR). The slew-rate (SR) decreases toward CT compared to RT. While the thermal noise floor also decreases, the low-frequency noise increases at CT. Overall, this leads to a slight decrease in the DAC’s noise performance at 4.6K.