A software-defined architecture and prototype for disaggregated memory rack scale systems

In order to improve the accuracy of silicon piezoresistance pressure sensor under different temperatures, temperature compensation should be carried out. A temperature compensation system of pressure sensors is presented. The structure, hardware and software design of the system are introduced. In the hardware design, MAX1452 is used as the main compensation unit. A curve fitting algorithm based on cubic B-spline is adopted in the temperature compensation software design. The accuracy and the production efficiency of the sensors are improved. The system features in low cost, high efficiency and high accuracy. And it has great spreading value

Abstract. The deformation monitoring of structures and buildings is an important task field of modern engineering surveying, ensuring the standing and reliability of supervised objects over a long period. Several commercial hardware and software solutions for the realization of such monitoring measurements are available on the market. In addition to them, a research team at the Neubrandenburg University of Applied Sciences (NUAS) is actively developing a software package for monitoring purposes in geodesy and geotechnics, which is distributed under an open source licence and free of charge. The task of managing an open source project is well-known in computer science, but it is fairly new in a geodetic context. This paper contributes to that issue by detailing applications, frameworks, and interfaces for the design and implementation of open hardware and software solutions for sensor control, sensor networks, and data management in automatic deformation monitoring. It will be discussed how the development effort of networked applications can be reduced by using free programming tools, cloud computing technologies, and rapid prototyping methods.

We present an efficient, high-throughput and scalable hardware design for accelerating the merge phase of the sort-merge join operation. Sort-merge join is one of the fundamental join algorithms and among the most frequently executed operations in relational databases. It has been the focus of various recent pieces of research, each having different shortcomings and usually only focusing on the sort phase. In this paper, a new parallel sort-merge join architecture is developed, that provides data streaming functionality and high throughput. The key idea of the paper is the use of a novel design for a co-grouping engine, with which the input data are summarised on-the-fly. In this way, the operation is performed on streams of data, preserving the linear access pattern for faster data movement and also eliminates the need for a replay buffer/cache. In contrast to related work, our approach does not make assumptions about the value distribution of the input data and applies to any input size and width. We evaluate the design on a Zynq UltraScale+ based platform, and show that there is up to 3.1 times speedup over the host processor, even without accelerating the sort phase, while still taking into account the data transfers from and to main memory in Linux.

In response to the advent of quantum computers, which pose significant threats to traditional cryptographic systems, NIST announced the quantum-resistant Module Lattice-based Key Encapsulation Mechanism (ML-KEM) and Digital Signature (ML-DSA) standards in August 2024. While prior studies have proposed hardware designs to accelerate either ML-KEM or ML-DSA individually, a unified architecture supporting all requirements of both schemes remains lacking. Leveraging the shared lattice-based cryptographic structures of ML-KEM and ML-DSA, this paper proposes a novel, high-performance architecture that supports all phases of both standards. The design allows flexible switching between operation modes and security levels at runtime, providing versatility and user-friendliness. Based on a long-term analysis of both cryptosystem theories, we propose optimizations in unified components, with specific configurations that execute both schemes efficiently in hardware while reducing redundant resource utilization from overlapping tasks. The timing diagram is carefully arranged to maximize concurrency, allowing the architecture to deploy multiple tasks in parallel, thereby addressing performance bottlenecks commonly seen in asymmetric cryptosystems. Moreover, we integrate several efficient countermeasure techniques to mitigate side-channel attack vulnerabilities in the hardware implementation. The proposed architecture is validated through implementation on Zynq UltraScale+ FPGA platform, demonstrating optimal execution times for each main algorithm in both post-quantum cryptography standards. Compared to state-of-the-art designs, our implementation exhibits superior performance and efficiency, as evaluated by the area-time product metric, as well as solves problems arising from outdated standards in previous studies.

This research is a continuation of previous work by the authors relating to the inclusion of aesthetic criteria within an interactive evolutionary design system. The work described extends the design system re the manipulation of a more complex design problem with increased importance placed on aesthetic criterion. The paper initially introduces the previous work before describing more recent research and positioning this in terms of previously published work. Finally, initial results from the further developed design system are presented.

Enterprises perceive a huge opportunity in mining information that can be found in big data. New storage systems and processing paradigms are allowing for ever larger data sets to be collected and analyzed. The high demand for data analytics and rapid development in technologies has led to a sizable ecosystem of big data processing systems. However, the lack of established, standardized benchmarks makes it difficult for users to choose the appropriate systems that suit their requirements. To address this problem, we have developed the BigBench benchmark specification. BigBench is the first end-to-end big data analytics benchmark suite. In this paper, we present the BigBench benchmark and analyze the workload from technical as well as business point of view. We characterize the queries in the workload along different dimensions, according to their functional characteristics, and also analyze their runtime behavior. Finally, we evaluate the suitability and relevance of the workload from the point of view of enterprise applications, and discuss potential extensions to the proposed specification in order to cover typical big data processing use cases.

Previous works have projected that the peak performance of FPGAs can outperform that of the general purpose processors. However, no work actually compares the performance between FPGAs and CPUs using the standard benchmarks such as the LINPACK benchmark. We propose and implement an FPGA-based hardware design of the LINPACK benchmark, the key step of which is LU decomposition with pivoting. We introduce a fine-grained pipelined LU decomposition algorithm that enables optimum performance by exploiting fine-grained pipeline parallelism. A scalable linear array of processing elements (PEs), which is the core component of our hardware design, is proposed to implement this algorithm. To the best of our knowledge, this is the first reported FPGA-based pipelined implementation of LU decomposition with pivoting. A total of 19 PEs can be integrated into an Altera Stratix II EP2S130F1020C5 on our self-designed development board. Experimental results show that the speedup up to 6.14 can be achieved relative to a Pentium 4 processor for the LINPACK benchmark.

Commercial cache-coherent nonuniform memory access (ccNUMA) systems often require extensive investments in hardware design and operating system support. A different approach to building these systems is to use Standard High Volume (SHV) hardware and stock software components as building blocks and assemble them with minimal investments in hardware and software. This design approach trades the performance advantages of specialized hardware design for simplicity and implementation speed, and relies on application-level tuning for scalability and performance. We present our experience with this approach in this paper. We built a 16-way ccNUMA Intel system consisting of four commodity four-processor Fujitsu® Teamserver™ SMPs connected by a Synfinity™ cache-coherent switch. The system features a total of sixteen 350-MHz Intel® Xeon™ processors and 4 GB of physical memory, and runs the standard commercial Microsoft Windows NT® operating system. The system can be partitioned statically or dynamically, and uses an innovative, combined hardware/software approach to support application-level performance tuning. On the hardware side, a programmable performance-monitor card measures the frequency of remote-memory accesses, which constitute the predominant source of performance overhead. The monitor does not cause any performance overhead and can be deployed in production mode, providing the possibility for dynamic performance tuning if the application workload changes over time. On the software side, the Resource Set abstraction allows application-level threads to improve performance and scalability by specifying their execution and memory affinity across the ccNUMA system. Results from a performance-evaluation study confirm the success of the combined hardware/software approach for performance tuning in computation-intensive workloads. The results also show that the poor local-memory bandwidth in commodity Intel-based systems, rather than the latency of remote-memory access, is often the main contributor to poor scalability and performance. The contributions of this work can be summarized as follows: • The Resource Set abstraction allows control over resource allocation in a portable manner across ccNUMA architectures; we describe how it was implemented without modifying the operating system. • An innovative hardware design for a programmable performance-monitor card is designed specifically for a ccNUMA environment and allows dynamic, adaptive performance optimizations. • A performance study shows that performance and scalability are often limited by the local-memory bandwidth rather than by the effects of remote-memory access in an Intel-based architecture.

The passive surface wave survey is a practical, non-invasive seismic exploration method that has increasingly been used in geotechnical engineering. However, in situ deployment of traditional wired geophones is labor intensive for a dense sensor array. Alternatively, stand-alone seismometers can be used, but they are bulky, heavy, and expensive because they are usually designed for long-term monitoring. To better facilitate field applications of the passive surface wave survey, a low-cost energy-efficient geophone system was developed in this study. The hardware design is presented in this paper. To validate the system’s functionality, both laboratory and field experiments were conducted. The unique feature of this newly-developed cableless geophone system allows for rapid field applications of the passive surface wave survey with dense array measurements.

Aerial seismology (AS) consists in detecting and characterizing atmospheric infrasound induced by ground displacements. Several studies have demonstrated that seismo-acoustic infrasound is highly similar to the seismic ground motion, making it a viable alternative for seismology on planetary bodies where deploying seismometers is technologically challenging. Until recently, such experiments were restricted to artificially-generated seismic events. However, on July 22, 2019, Brissaud et al. detected for the first time the infrasonic signature of a magnitude 4.2 earthquake from a high-altitude solar-heated balloon. In order to further demonstrate the feasibility of AS, additional detections are needed. Using similar balloons and payloads, stratospheric flights were launched several times per week during the summer of 2021 over Oklahoma’s seismogenic zone. In this work, we present this campaign and its initial results. We describe the flight system, instrumentation, and details of the campaign design. We focus on the possible detections of earthquakes during the campaign using numerical simulations. For selected events, we present the balloon pressure data and extract potential arrivals. We perform full-waveform simulations using SPECFEM2D-DG to confirm those arrivals. We conclude with statistical arguments for earthquake detections and recommendations for future flights. Earthquakes are numerous in Oklahoma, but are of low and decreasing magnitudes. Nonetheless, this campaign’s dataset is unique for the development of AS.

This paper presents architecture independent characterization of embedded Java workloads based on the industry standard GrinderBench benchmark which includes different classes of real world embedded Java applications. This work is based on a custom built embedded Java virtual machine (JVM) simulator specifically designed for embedded JVM modeling and embodies domain specific details such as thread scheduling, algorithms used for native CLDC APIs and runtime data structures optimized for use in embedded systems. The results presented include dynamic execution characteristics, dynamic bytecode instruction mix, application and API workload distribution, object allocation statistics, instruction-set coverage, memory usage statistics and method code and stack frame characteristics.

Testing is an important and challenging part of software development and its effectiveness depends on the quality of test cases. However, there exists no means of measuring quality of tests developed for GPU programs and as a result, no test case generation techniques for GPU programs aiming at high test effectiveness. Existing criteria for sequential and multithreaded CPU programs cannot be directly applied to GPU programs as GPU follows a completely different memory and execution model. We surveyed existing work on GPU program verification and bug fixes of open source GPU programs. Based on our findings, we define barrier, branch and loop coverage criteria and propose a set of mutation operators to measure fault finding capabilities of test cases. CLTestCheck, a framework for measuring quality of tests developed for GPU programs by code coverage analysis, fault seeding and work-group schedule amplification has been developed and evaluated using industry standard benchmarks. Experiments show that the framework is able to automatically measure test effectiveness and reveal unusual behaviours. Our planned work includes data flow coverage adopted for GPU programs to probe the underlying cause of unusual kernel behaviours and a more comprehensive work-group scheduler. We also plan to design and develop an automatic test case generator aiming at generating high quality test suites for GPU programs.

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. Methods in the first group (e.g., software instrumentation), can be accurate but have unacceptable overheads and offer no insight into the interaction of the software and the hardware. Methods in the second group (e.g., hardware supported) run in real time and connect code to the response in the architecture, at a considerable decrease in accuracy, with a high degree of specificity to the hardware and therefore with limited actionable information made available. In this work, we focus on the latter group - the collection and analysis of raw performance data sourced from hardware Performance Monitoring Units, built into the majority of processors. The periodic collection of samples (Event Based Sampling), containing code locations, for instance, can be triggered on events such as retired instructions or cache misses. We quantify accuracy improvements to existing methods, propose a better performing method of performance data collection and a new architecture-agnostic method of performance data analysis. In our experiments, we analyze compiled, large-scale production workloads, industry standard benchmarks, and micro-benchmarks reproducing specific architectural behaviors. First, we focus on performance data collection methods and their accuracy, when establishing instruction retirement rates. These vary from least to most advanced and we examine the low level factors influencing accuracy. In particular, we employ a method based on Last Branch Records, a hardware facility present on some Intel architectures, which allows for the sampling of short records of last taken branches leading up to the sample. We compare the most commonly used method, its improved derivatives and the Last Branch Record based method. With respect to the first method, we observe accuracy improvements of up to 18x on synthetic benchmarks and 15x on real applications. Second, to further improve accuracy, we propose a new collection method named Hybrid Basic Block Profiling, fusing those based on Last Branch Records and the widely used Event Based Sampling. We apply simple machine learning techniques to determine the operating criteria. As a demonstration of capability, our method and a profiling tool are used to generate Instruction Mixes, which traditionally require good quality data at the most detailed level of granularity - basic blocks. Compared to software instrumentation, we observe an improvement in runtime of up to 76x, while keeping instruction attribution errors at 2.1% on average. In our third contribution we describe an architecture-agnostic performance analysis methodology called Hierarchical Cycle Accounting. The user is presented with a navigable hierarchy of microarchitectural issues, expressed in a metric that is universal and simple to compare - core cycles. We develop a reference implementation for the Intel Ivy Bridge microarchitecture and provide pointers for implementations on other processor architectures. Our approach and tool are successfully used by non-experts to improve and vectorize complex scientific code. Experts benefit as well - by being able to pinpoint software issues undetected by other methods, and identifying a bug in a family of Intel processors.

Programmers usually rely on cache performance data to optimize their applications towards high runtime cache hit ratio. In this paper, we introduce a software toolset CacheIn, which uses simulation and monitoring to collect comprehensive cache performance data. CacheIn consists of a cache simulator for modeling the cache activities, a cache monitor for gathering different kind of information, and a multilayer software infrastructure for processing the raw monitoring data towards statistical, high-level representations, like histograms and summarized numbers. CacheIn exhibits both the details of traditional software mechanisms and the feasibility of performance counters. Based on a code instrumentor, we have verified CacheIn using standard benchmarks. Initial experimental results show its full functionality in terms of providing accurate, comprehensive, and corse-grained performance data.KeywordsMemory ReferenceCache LineMemory HierarchyPerformance CounterSoftware InfrastructureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper describes the changing environment of large-scale hardware designs as influenced by technology advancements and the growing use of design verification in the design implementation process. The design verification methodology presented here saved some 66% from the 3081 product schedule, when compared with a schedule utilizing a conventional verification method, on almost 800 000 LSI logic circuits. The paper discusses the use of software modeling techniques to verify LSI hardware designs, methods used for deciding when modeling should be stopped and hardware can be built with sufficient assurance to permit additional verification to continue on the hardware, methods for testing the hardware as it is assembled into a very large processor complex, and the organization of the design verification system to avoid duplicate creation of test cases for different stages of the design process. Experiences encountered in designing and verifying the 3081 system, a discussion of some shortcomings, and an endorsement of certain techniques and improvements for use in future designs are also presented.