Experience with building a commodity Intel-based ccNUMA system

The hardware design of Godson-3A processor adopts the scalable distributed multi-core structure which is based on a 2D mesh. It can make use of multi-chip interconnection to construct a unified topology structure for board level or system level. This kind of interconnected system can't achieve entirely by hardware design, and it also needs the reasonable design of the BIOS and upper software. As the only bridge between hardware and software, the BIOS plays an important role in the computer system. In this paper, we introduce the two-level scalable architecture implemented inside Godson-3A, and discuss the realization of software routing configuration mechanism by the crossbar switch in detail. Based on the above analysis, we analyze the design and implementation of BIOS in a CC-NUMA system composed by multiple processors with support of Godson-3A hardware design, and in a larger NCC- NUMA system formed by multiple CC-NUMA systems.

HW/SW co-emulation technique combing software simulation with hardware acceleration is one of the popular techniques for SOC verification, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation technique is proposed and presented in the paper. In the proposed technique, software side executes, sends stimulus data and receives response data continuously while hardware side is testing SUT and generating response data in parallel. Experiment result demonstrates that, compared to interrupt-based communication mode, stream-based communication mechanism can improve communication throughput by more than 10 times.

The environment for high-performance computing is changing rapidly. On the hardware side, chip-related advances such as copper metallization, siliconon-insulator, and high-resolution lithography will continue to contribute to rapid increases in device speed. Although the investments needed continue to grow, we don’t see any fundamental roadblocks during the next ten years. With higher levels of integration, the importance of packaging grows, and IBM has paid quite a bit of attention to this. On the software side, the changes brought about by an increased interest in Open Source promises to fundamentally lower the capital requirements for the introduction of new platforms and to affect the computer industry in many other ways as well.

Reliability considerations had little influence in the design of the first generation of computers. Notable exceptions being, on the hardware side, some circuitry incorporated into the UNIVAC I for checking purposes, and on the software side, the frequency counts employed by von Neumann and Goldstine for measurement purposes. The second generation of computers witnessed a wider interest in hardware reliability while essentially ignoring the software reliability problem. Current computer systems (e.g., IBM/370) incorporate elaborate hardware reliability considerations in their design while continuing to ignore reliable software design.

An integrated QR-based identification and multi-participant quiz system is developed for classroom and competition scenarios. It reduces the check-in latency, removes fixed buzz-in timing, and lifts hardware-imposed limits on the participant count. On the software side, a MATLAB-R2022b-based module integrates the generation and recognition of linear barcodes and QR Codes, enabling fast, accurate acquisition of contestant information while reducing the latency and error risk of manual entry. On the hardware side, control circuits for compulsory and buzz-in modules are designed and simulated in Multisim-14.3. To accommodate diverse scenarios, the team-versus-team buzz-in mode is extended to support two- or three-member teams. Functional tests demonstrate the stable display of key states—including contestant identity, buzz-in priority group ID, and response duration. Compared with typical MCU-channel-based designs, the proposed system relaxes hardware-channel constraints, decoupling the participant count from fixed input channels. It also overcomes fixed-timing limitations by supporting scenario-dependent configuration. The Participant Information Registration subsystem achieved a mean accuracy of 86.7% and a mean per-sample computation time of 14 ms. The 0–99 s configurable timing aligns with question difficulty and instructional procedures. It enhances fairness, adaptability, and usability in formative assessments and competition-based learning.

This design has realized a new granary temperature wireless measurement node by hardware and software. On the hardware side, the node is composed of MCU, power supply, wireless RF module, combined buttons, watchdog and sensors in the temperature measurement cables. On the software side, design has realized real-time detection temperature and power supply voltage, build sensor topology, wireless reporting and abnormal alarming. Its acquisition accuracy is 0.625 degrees Celsius, meets the requirements. Design reduces power consumption by frequent acquisition temperature and periodically reporting, ensures the communication stability by clock synchronization and communication back-off principle. Proved by practice, it has a certain practical value for monitoring the grain situation.

Industrial machines are generally expensive to implement due to their requirement of being fast and robust. In this paper, we proposed a new approach to the problem, particularly, a walnut sorting machine that was built cheaply using open solution. On hardware side, we used readily available electronics and on the software side, Robot Operating System was adopted to handle low level hardware abstraction. Machine Learning, Computer Vision and data processing techniques were implemented on top of them using high level programming language. This resulted in a highly functional, easy to maintain yet inexpensive walnuts sorting machine - which was confirmed by our Austrian partner’s testing. This success, hopefully, will pave the way for more projects using similar approaches.

The energy consumption of supercomputers is one of the critical problems for the upcoming Exascale supercomputing era. The awareness of power an energy consumption is required on both software and hardware side. This poster deals with the energy consumption evaluation of the Total-Finite Element Tearing and Interconnect (TFETI) based solvers [2] of linear systems implemented in PERMON toolbox [1], which is an established method for solving real-world engineering problems, and with the energy consumption evaluation of the BLAS routines. The experiments performed in the poster deal with CPU frequency. This work is performed in the scope of the READEX project (Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing) [6]. The measurements were performed on the Intel Xeon E5-2680 (Intel Haswell micro-architecture) based Taurus system installed at TU Dresden. The system contains over 1400 nodes that have an FPGA-based power instrumentation called HDEEM (High Definition Energy Efficiency Monitoring), that allows for fine-grained and more accurate power and energy measurements. The measurements can be accessed through the HDEEM library, allowing developers to take energy measurements before and after the region of interest. We have evaluated the effect of the CPU frequency on the energy consumption of the TFETI solver for a linear elasticity 3D cube synthetic benchmark. On the dualized problem MPFX=MPd, we have evaluated the effect of frequency tuning on the energy consumption of the essential processing kernels of the TFETI method. There are two main phases in TFETI — preprocessing and solve. In preprocessing it is necessary to regularize the stiffness matrix K and factorize it and to assemble the G and GGT matrices and the second one to factorize. Both operations belong to the most time and also energy consuming operations. The solve employs the Preconditioned Conjugate Gradient (PCG) algorithm, which consists of sparse matrix-vector multiplications (by F, P, M L , M D matrices) and vector dot products and AXPY functions. In each iteration, we need to apply the direct solver twice, i.e., for forward and backward solves for the pseudoinverse K+ action and for the coarse problem solution, the (GGT)−1 action. The multiplication by the dense Schur complement matrix adds an additional operator with different computational characteristics, potentially increasing the exploitable dynamism. The poster provides results for two types of frequency tuning: (1) static tuning and (2) dynamic tuning. For static tuning experiments, the frequency is set before execution and kept constant during the runtime. For dynamic tuning, the frequency is changed during the program execution to adapt the system to the actual needs of the application. The poster shows that static tuning brings up 11.84% energy savings when compared to default CPU settings (the highest clock rate). The dynamic tuning improves this further by up to 2.68%. In total, the approach presented in this paper shows the potential to save up to 14.52% of energy for TFETI based solvers, see Table1. Another energy consumption evaluations were done with selected Sparse and Dense BLAS Level 1, 2 and 3 routines. For benchmarking we have used a set of matrices from University Florida collection [4]. We have employed AXPY, Sparse Matrix-Vector, Sparse MatrixMatrix, Dense Matrix-Vector, Dense Matrix-Matrix and Sparse Matrix-Dense Matrix multiplication routines from Intel Math Kernel Library (MKL) [3]. The measured characteristics illustrate the different energy consumption of BLAS routines, as some operations are memory-bounded and others are compute-bounded. Based on our recommendations one can explore dynamic frequency switching to achieve significant energy savings up to 23%, for more details see Table 2.

This book presents cutting-edge emerging technologies and approaches in the areas of service-oriented architectures, intelligent devices and cloud-based cyber-physical systems. It provides a clear view on their applicability to the management and automation of manufacturing and process industries. It offers a holistic view of future industrial cyber-physical systems and their industrial usage and also depicts technologies and architectures as well as a migration approach and engineering tools based on these. By providing a careful balance between the theory and the practical aspects, this book has been authored by several experts from academia and industry, thereby offering a valuable understanding of the vision, the domain, the processes and the results of the research. It has several illustrations and tables to clearly exemplify the concepts and results examined in the text and these are supported by four real-life case-studies. We are witnessing rapid advances in the industrial automation, mainly driven by business needs towards agility and supported by new disruptive advances both on the software and hardware side, as well as the cross-fertilization of concepts and the amalgamation of information and communication technology-driven approaches in traditional industrial automation and control systems. This book is intended for technology managers, application designers, solution developers, engineers working in industry, as well as researchers, undergraduate and graduate students of industrial automation, industrial informatics and production engineering.

We live in an era where typical measures towards the mitigation of environmental degradation follow the identification and recording of natural parameters closely associated with it. In addition, current scientific knowledge on the one hand may be applied to minimize the environmental impact of anthropogenic activities, whereas informatics on the other, playing a key role in this ecosystem, do offer new ways of implementing complex scientific processes regarding the collection, aggregation and analysis of data concerning environmental parameters. Furthermore, another related aspect to consider is the fact that almost all relevant data recordings are influenced by their given spatial characteristics. Taking all aforementioned inputs into account, managing such a great amount of complex and remote data requires specific digital structures; these structures are typically deployed over the Web on an attempt to capitalize existing open software platforms and modern developments of hardware technology. In this paper we present an effort to provide a technical solution based on sensing devices that are based on the well-known Arduino platform and operate continuously for gathering and transmitting of environmental state information. Controls, user interface and extensions of the proposed project rely on the Android mobile device platform (both from the software and hardware side). Finally, a crucial novel aspect of our work is the fact that all herein gathered data carry spatial information, which is rather fundamental for the successful correlation between pollutants and their place of origin. The latter is implemented by an interactive Web GIS platform operating oversight in situ and on a timeline basis.

In the past three years, the so-called second wave of Virtual Reality (VR) has brought us a vast amount of new displays and input devices. Not only new hardware has entered the consumer market providing affordable pricing models but also completely new technologies are being designed and developed. Additionally new concepts for handling existing problems on the hardware and software side of the VR technology are constantly being introduced. This software and hardware development is mainly lead by enthusiasts interested in the domain of VR opposed to the established scientific community, which already partially makes use of the newly available technology. Besides Head-Mounted Displays (HMDs), either cable-based or mobile, other devices like haptics devices, controllers, vests, omnidirectional treadmills, tracking technologies, as well as optical scanners for gesture-based interaction are gaining importance in the field of commodity VR. Most of these technologies are already precise and robust enough to be used for professional operation and scientific experiments. The topics discussed are the common issues with the new technologies including the approaches to solve them as for example motion-to-photon latency, barrel distortion, and low-persistence displays. Additionally an in-depth analysis of the available solutions expected to hit the market is provided. A taxonomy categorising the current developments with the chosen implementation approaches will be given. The paper analyses the state of technological advancements in the field and provides an extensive overview on the current development considering the upcoming devices and the advancements from the software side.

A new generation of high performance programmable digital signal processors has a highly integrated parallel architecture, incorporating special purpose hardware features, on-chip memory, and multiple processors into a single chip. Such single chip multiprocessor DSPs, however, require a sophisticated performance monitoring tool to achieve maximum performance. The authors discuss the requirements and functionality of performance monitoring tools suitable for single chip multiprocessor DSPs. Specifically, they describe a performance monitoring tool that satisfies these requirements and functionality: the MVP Performance Monitor, developed for the Texas Instruments' TMS320C80 Multimedia Video Processor. They present an overview of the MPM and a general performance tuning approach using the MPM. An 8/spl times/8 block based 2D discrete cosine transform (DCT) implementation demonstrates the MPM's effectiveness. The authors achieved an overall speedup of 4.67 by tuning the performance based on the monitoring results from the MPM.

Overhead analysis was developed as a performance tuning approach for parallel programming and were adopted by several performance analysis systems for OpenMP programs. In this paper, an extended overhead analysis scheme based on layered model is proposed for OpenMP programming, to further enhance the capability of overhead analysis and thus make the OpenMP performance tuning easier. An example case called ILP/TLP overlap is studied in detail to show the idea of layered overhead model, and a new way to organize the overhead hierarchically is also presented based on the layered overhead model.KeywordsLayered ModelPerformance TuningChunk SizeAbstract LayerThread Level ParallelismThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this project a system design and implementation has made for allowing usage of Near Field Communication (NFC) enabled devices securely. In order to make the design appropriate to NFC standards, primarily an implementation environment infrastructure has been built. Additionally, the method of hardware & software codesign is operated. At the stage of implementing hardware side; FPGA is used for implementing necessary cryptographic algorithms. At the stage of implementing software side; the order of the protocol flow and two-way communication is implemented for secured NFC protocol by controlling cryptographic algorithms which are implemented at the hardware side.

This article proposes an approach for performance tuning of model predictive control (MPC) using goal-attainment optimisation of the cost function weighting matrices. The approach is developed for three formulations of the control problem: (i) minimal and (ii) non-minimal design based on the same cost function and (iii) a non-minimal MPC approach with an explicit integral-of-error state variable and modified cost function. This approach is based on earlier research into multi-objective optimisation for proportional-integral-plus control systems. Simulation experiments for a 3-input, 3-output Shell heavy oil fractionator model illustrate the feasibility of MPC goal attainment for multivariable decoupling and attainment of a specific output response. For this example, the integral-of-error state variable offers improved design flexibility and hence, when it is combined with the proposed tuning method, yields an improved closed-loop response in comparison to minimal MPC.