A Statistical Submodule Open-Circuit Failure Diagnosis Method for Modular Multilevel Converters (MMCs) With Variance Measurement

With the increasing application of the modular multilevel converter (MMC), diagnosis of submodule (SM) open-circuit failures is becoming a popular topic. SM open-circuit failure diagnosis normally requires failure detection and failure localization. Almost all existing SM open-circuit failure diagnosis methods execute failure detection and failure localization separately. This not only complicates the diagnosis process, but also results in longer diagnosis time. In this paper, an SM open-circuit failure diagnosis method enabling combined failure detection and localization is proposed. The proposed method is established based on the characteristics that capacitor voltages of faulty SMs variate differently from those of normal SMs. A quantification index of capacitor voltage variation is first proposed. By evaluating the corresponding index values of all SMs with the quartile analysis, failure detection and localization can be implemented simultaneously. What’s more, the quartile analysis results can also identify faulty switching devices in the SM, which provides more flexibility for failure tolerant control. The proposed method performs relatively easy and requires no extra hardware resources. Meanwhile, both single and multiple failures can be properly handled whether faulty SMs are in the same or different arms. Besides, the proposed method is immune to parameter uncertainties owing to its statistical property. Experimental results under various failure scenarios are presented to verify the effectiveness of the proposed method.

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

Submodule (SM) fault detection and location (FDL) is essential for the reliable operation of modular multilevel converters (MMCs). Once SM failures occur, the capacitor voltages of faulty SMs will be out of control and deviate from the rated value. As analyzed in this paper, in normal state, the charging abilities of driving signals are constant in one fundamental period. Thus, the voltage variation of SMs in one fundamental period should coincide with the charging ability of driving signals applied to them. So this paper proposes an FDL method based on the capacitor voltage variation observations, which monitors the health state of SMs by comparing the expected voltage variations with the measured ones. The proposed method can detect and locate the faulty SM simultaneously in no more than two fundamental periods and requires no arm current measurement. Effectiveness of the proposed method and influence of capacitance inconsistency are validated by simulation results of a three-phase 101-level MMC in MATLAB/Simulink.

Submodule (SM) failure detection and localization is crucial to reliability improvement of modular multilevel converters (MMCs), which consist of numerous identical SMs. Upon SM failures, the capacitor voltages of the faulty SMs deviate from those of the healthy SMs. Hence, SM voltage consistency disruption can be utilized as an indicator of SM failures. To enable effective consistency evaluation of numerous SM voltages, the single ring theorem, which is an ideal analyzing tool for large size matrices, is applied to SM failure detection in this paper. The proposed SM failure detection method eliminates the need for ideal-state estimators and thus ensures sufficient robustness in terms of parameter uncertainties. Additional voltage/current sensors are not required, which is beneficial for cost efficiency. A statistical-analysis-based SM failure localization method enabling fast identification of the faulty SMs upon failure detection is also proposed. Both single and multiple SM failure detection and localization can be handled with the proposed method even if the faulty SMs are in different arms. The effectiveness of the proposed SM failure diagnosis method is verified by both simulation in MATLAB/Simulink and experimentation on a 13-level MMC prototype.

— The modular multilevel converter (MMC) is considered to be emerging multilevel topology for medium to high power applications due to its modularity and highly reliable structure. However, large submodule (SM) capacitor voltage ripple and higher circulating current during variable frequency operation is the major drawback of the MMC. In the literature, higher-order harmonic elimination technique is presented to reduce SM capacitor voltage ripple and circulating current. In this article, effect of lower-order harmonics on circulating current is investigated. The effect of second-order fundamental frequency current harmonic I2f on arm inductor is analyzed. Based on detailed analysis, an optimal design method for selection of arm inductor is proposed. Proposed optimal design is capable of reducing the circulating current under variable frequency range as well as SM capacitor voltage ripple remains under specified limit during entire variable frequency operation. A detailed MATLAB model of MMC fed high power medium voltage drive is developed. Experimental setup is also developed to check the effectiveness of proposed optimal design method. Reduction in circulating current and control of SM capacitor voltage ripple is observed for entire range of frequency.

The modular multilevel converter (MMC) in high voltage direct current (HVDC) is equipped with hundreds of sub-modules (SMs), so the detailed model consist of hundreds of switching devices and consequently large computational effort but mathematical converter model with Arm Level Averaged (ALA) allows to know the dynamic and converter control decreasing simulation time. This paper presents a control strategy decou- pling the modulation index implemented in MMC-ALA model, it allows MMC operation with variable DC bus voltage but keeping constant the capacitor voltage in upper and lower arms, the evaluations consider the next operations: boost mode reducing DC bus voltage to 0.5.p.u., DC fault and SM voltage increased. The upper and lower capacitor voltages in all cases follow the reference independently to DC bus voltage value, the strategy is simulated in 150 MW converter using Matlab/Simulink.

Summary form only given. The modular multilevel converter (MMC) is a potential candidate for medium/high-power applications, specifically for high-voltage direct current (HVDC) transmission systems. One of the technical challenges associated with the control of an MMC is to carry out the submodule (SM) capacitor voltages balancing task without imposing any unnecessary switching transition among the SMs. This paper develops a general framework for the capacitor voltage balancing of an MMC. Based on the developed framework and with the objective of reducing the unnecessary switching transitions among the SMs, three capacitor voltage-balancing strategies are proposed and investigated: 1) a slow-rate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy which combines a predictive method with the conventional sorting method; and 3) a fundamental-frequency balancing strategy. Performance of the proposed strategies for a point-to-point 21-level MMC-based HVDC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capability and tradeoffs of the proposed strategies to reduce the number of switching transitions and, consequently, the MMC losses, under various conditions.

The modular multilevel converter (MMC), used in high-voltage dc applications, consists of hundreds of submodules in each arm. The operation and control of the MMC require sensing of the capacitor voltage of each submodule. The transmission of the sensed data from hundreds of submodules over individual channels leads to wiring complexity. This work suggests that time-multiplexing can be used to transmit the sensed data of multiple submodules across a common serial interface bus. Time multiplexing, however, decreases the sampling rate. Since the submodule capacitor voltage has both ac and dc components, an adequate sampling rate must be maintained to avoid the aliasing of ac components. In this article, an estimation scheme is investigated for reconstructing the ac components of the submodule capacitor voltages within the processing platform, leaving just the dc component to be transmitted over the common bus. The mathematical analysis of the data transmission system and proposed estimation scheme is performed, and the influence on the closed-loop performance is studied. The proposed scheme is experimentally verified in the laboratory.

Unlike the modular multilevel converter (MMC) topology operated under the rectifier or inverter modes, control of the balanced state for the submodule (SM) capacitor voltage has emerged as the key issue for DC-DC MMCs. This is mainly caused by no balanced alternative powers being used for balancing SM capacitor voltages, which can be absorbed from the input or output DC sides of the converter. Typically, the alternative voltages and currents should be injected to achieve SM capacitor voltage balance in the DC-DC MMC. However, this solution is based on the cost of adopting the bulky LC filter components. For interconnecting different DC voltages in medium-voltage applications, this paper presents a non-isolated DC-DC MMC equipped with the proposed middle cells. It is intended to achieve DC voltage conversion without adopting bulky passive LC filters. On the one hand, the alternative currents, used for balancing the SM capacitor voltages, are arranged for flowing only within the phase legs of the proposed DC-DC MMC without disturbing the input current. On the other hand, through appropriate control of the middle cells, compensated components can be developed to eliminate the undesirable voltages on the output DC side. The middle cells of the proposed DC-DC MMC are supplied with the function of the active filter, which enables the DC-DC MMC system to escape the bulky LC components. Through theoretical analysis and a control strategy, the proposed DC-DC MMC has been analyzed comprehensively. Finally, the simulation and experimental results are verified to evaluate the effectiveness of the proposed DC-DC MMC.

Modular Multilevel Converter (MMC) has been widely used in medium/high voltage direct current transmission, motor drive, and renewable energy power generation, etc. The reliability requirements of MMC system which is composed of sub-modules(SM) as building blocks, are getting crucial. However, the testing for reliability of SMs in a full MMC system is time consuming and costly. In this paper, a mission profile emulator for SMs in MMC system is therefore focused, by using this mission profile emulator, the SMs can be tested individually without building a full MMC system. Simulation results show that the mission profiles of the SM under test is well agrees with the SM in a complete MMC system.

ABSTRACTThe modular multilevel converter (MMC) has attracted significant attention in the fields of high and medium‐voltage applications in recent years. Traditional indirect finite control set model predictive control (IFCS‐MPC) strategies for MMC require voltage measurements from each submodule (SM) for the voltage control loop. As a result, a considerable number of sensors is required to achieve energy balancing, leading to increased circuit complexity and higher hardware costs. This paper proposes an IFCS‐MPC method for MMC with a reduced number of sensors approach. In the approach, an SM capacitor voltage observer is designed based on the discrete‐time model of capacitor voltage, utilizing the measured arm current and SM switching state. Only one SM voltage sensor is needed per arm, which is used to correct the observed voltage errors caused by the discrete‐time model and the accuracy of the parameters. Subsequently, the observed values of the SM capacitor voltages are substituted for the measured values in the voltage sorting algorithm of IFCS‐MPC to reduce voltage sensors. The simulation and experiment results are carried out to demonstrate the effectiveness of the proposed control system and the feasibility of reducing the number of sensors.

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system.

The modular multilevel converter (MMC) is emerged as the most favourable multilevel converter topology for medium to high-voltage applications. Reliability is one of the major concerns in an MMC due to high fragile component count. Due to low-cost and high energy density, electrolytic capacitors (ECs) are usually preferred as floating capacitors in the MMC. However, the ECs are gradually degraded over the time due to inherent chemical processes, which results in a decrease in capacitance value. This results in an increase in voltage ripple across the SM capacitors and would distort the output waveforms. Moreover, the prolonged use of these aged capacitors could disrupt the MMC operation. Therefore, monitoring and failure detection of submodule (SM) capacitors in an MMC are pivotal to enhance the reliability. This paper presents an SM capacitance estimation strategy for an MMC using nearest level modulation (NLM). A modified voltage balancing control structure with NLM is presented to reduce the unbalance in the capacitor voltages. The proposed approach uses available hardware for converter control with easy implementation in the same controller. Extensive studies are conducted on a three-phase MMC in PLECS simulation platform. Furthermore, experimental results are presented to substantiate the effectiveness of the proposed approach.

Submodule (SM) fault diagnosis is necessary for the reliability of modular multilevel converters (MMC) and the complex operating environment of MMC may cause missing data and noise in signal detections, where some of the existing open circuit fault diagnosis methods can be disabled. An artificial intelligence (AI) diagnosis method for open circuit faults in MMC based on extreme gradient boosting system (XG-Boost) is proposed in this paper which can diagnose the open circuit fault quickly and accurately in the mentioned conditions. Compared with neural network diagnosis method, the proposed method has higher accuracy with the same non-ideal data. Faster speed and better processing ability of the proposed method are also validated by simulation of a three-phase MMC in MATLAB/Simulink.

The modularity, fault-tolerability, and voltage scalability features allow the modular multilevel converter (MMC) to be a promising topology for modern electric ship applications. Arm voltage and submodule (SM) capacitor voltage balancing controllers with conventional high-frequency modulation schemes are indispensable for reliable and stable operation of an MMC. This requires an additional external arm controller and the control complexity increases for an MMC with a large number of SMs. Alternatively, the space-vector pulse width modulation (SVPWM) schemes provide more freedom in selecting the voltage vectors to achieve multiple objectives, thus eliminating the arm voltage balancing controller. In this paper, a simplified SVPWM implementation for an $n$ -level MMC is proposed. This scheme utilizes all the available switching states and calculates switching timings by mapping to a two-level space-vector structure. The computational burden of the proposed scheme is independent of converter voltage level, therefore it is computationally efficient and well suited to the MMC with any number of SMs. Experimental results are presented to show the performance of an MMC system using the proposed scheme under steady-state, rapid acceleration and speed-reversal conditions.