Control Strategy Implemented in Modular Multilevel Converter to Improve the Operation During Variable DC Bus Voltage

Submodule (SM) fault detection and location (FDL) is essential for the reliable operation of modular multilevel converters (MMCs). Once SM failures occur, the capacitor voltages of faulty SMs will be out of control and deviate from the rated value. As analyzed in this paper, in normal state, the charging abilities of driving signals are constant in one fundamental period. Thus, the voltage variation of SMs in one fundamental period should coincide with the charging ability of driving signals applied to them. So this paper proposes an FDL method based on the capacitor voltage variation observations, which monitors the health state of SMs by comparing the expected voltage variations with the measured ones. The proposed method can detect and locate the faulty SM simultaneously in no more than two fundamental periods and requires no arm current measurement. Effectiveness of the proposed method and influence of capacitance inconsistency are validated by simulation results of a three-phase 101-level MMC in MATLAB/Simulink.

Modular multilevel converter (MMC) based high voltage direct current (HVDC) systems are quite popular in high power transmission systems as it offers low losses, high quality output voltage, modular and scalable structure as compared to the two level voltage source converter based HVDC systems. However, inability to block dc fault current is a major concern of conventional MMC-HVDC system, especially for the overhead HVDC system. In this paper, the performance of conventional MMC with half bridge submodules is analyzed for dc side fault. In the event of a dc side fault, the conventional MMC acts as an uncontrolled diode rectifier and feeds very high current to dc fault. To tackle this problem, different techniques have been discussed in the literature. This paper gives a brief overview of dc fault tolerant techniques discussed in the literature. Moreover, in this paper, a detailed comparison between different hybrid topologies with dc fault tolerant capability is performed on the basis of required number of switches and capacitors. Furthermore, the fault tolerant capability of MMC with bipolar (full bridge) submodule is experimentally validated.

Summary form only given. The modular multilevel converter (MMC) is a potential candidate for medium/high-power applications, specifically for high-voltage direct current (HVDC) transmission systems. One of the technical challenges associated with the control of an MMC is to carry out the submodule (SM) capacitor voltages balancing task without imposing any unnecessary switching transition among the SMs. This paper develops a general framework for the capacitor voltage balancing of an MMC. Based on the developed framework and with the objective of reducing the unnecessary switching transitions among the SMs, three capacitor voltage-balancing strategies are proposed and investigated: 1) a slow-rate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy which combines a predictive method with the conventional sorting method; and 3) a fundamental-frequency balancing strategy. Performance of the proposed strategies for a point-to-point 21-level MMC-based HVDC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capability and tradeoffs of the proposed strategies to reduce the number of switching transitions and, consequently, the MMC losses, under various conditions.

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

The modular multilevel converter (MMC) is emerged as the most favourable multilevel converter topology for medium to high-voltage applications. Reliability is one of the major concerns in an MMC due to high fragile component count. Due to low-cost and high energy density, electrolytic capacitors (ECs) are usually preferred as floating capacitors in the MMC. However, the ECs are gradually degraded over the time due to inherent chemical processes, which results in a decrease in capacitance value. This results in an increase in voltage ripple across the SM capacitors and would distort the output waveforms. Moreover, the prolonged use of these aged capacitors could disrupt the MMC operation. Therefore, monitoring and failure detection of submodule (SM) capacitors in an MMC are pivotal to enhance the reliability. This paper presents an SM capacitance estimation strategy for an MMC using nearest level modulation (NLM). A modified voltage balancing control structure with NLM is presented to reduce the unbalance in the capacitor voltages. The proposed approach uses available hardware for converter control with easy implementation in the same controller. Extensive studies are conducted on a three-phase MMC in PLECS simulation platform. Furthermore, experimental results are presented to substantiate the effectiveness of the proposed approach.

Modular multilevel converter (MMC) has been widely used in high-voltage direct current (HVDC) transmission system due to its advantages of modularity, low switching frequency and excellent output voltage waveforms. Proper operation of MMC is based on capacitor voltage balancing. Conventional MMC capacitor voltage balancing control needs a large number of voltage sensors and sorting algorithm which increases computing burden on the processor. In this paper, a capacitor voltage self-balancing MMC with DC fault ride-through capability is proposed. Capacitor voltage balancing control of this proposed MMC is significantly simple due to its self-balancing auxiliary circuit. Sorting algorithm is not needed, each phase leg only needs one voltage sensor for top SM. So control complexity and computing burden are reduced greatly. Furthermore, DC fault ride-through capability is also reserved. Simulation results validates capacitor voltage of this new MMC topology can be well balanced and DC fault ride-through capability is effective.

Submodule (SM) open-circuit failures severely affect the reliable operation of modular multilevel converter (MMCs). A comprehensive SM open-circuit failure diagnosis process includes three steps with failure detection, localization, and classification. However, the existing diagnosis methods perform these steps separately, which makes the diagnosis process complicated. Furthermore, the efficiency is relatively low with separate diagnosis steps. To address this issue, a diagnosis method with variance measurement is proposed in this paper to combine failure detection, localization, and classification. The proposed method makes use of two fault characteristics of SM open-circuit failures: 1) SM capacitor voltages have distinct distributions upon different faulty IGBTs; 2) Numerous SMs in the MMC make the failure diagnosis equivalent to statistical outlier analysis. On account of the fault characteristics, a variance-based index called VAR is proposed to evaluate the distributions of SM capacitor voltages. The VAR values are then analyzed with quartile analysis, which is a statistical outlier analysis method, to complete the diagnosis process. The proposed failure diagnosis method features high reliability, high compatibility, and high cost-effectiveness. Finally, the feasibility of the proposed method is verified through both simulations and experiments under various failure scenarios.

Although the modular multilevel converters (MMCs) that contain submodules (SMs) with negative voltage capability have various advantages, they usually demand many more semiconductors than the conventional half-bridge SM-based MMC (HB-MMC). This study proposes a unidirectional-current clamp-double submodule (UC-CDSM) by combining two unidirectional-current full-bridge SMs (UC-FBSMs) using a shared switching device. The sharing design enables the UC-CDSM-based MMC (UC-CD-MMC) to have 25% fewer switching devices compared with the UC-FBSM-based MMC. The quantity of switching devices is rather similar to that in a conventional HB-MMC while the UC-CD-MMC still retains the advantages, such as low capacitor usage, dc fault clearing capability, and wide-range dc voltage adjustability. Moreover, a unidirectional-current hybrid MMC composed of UC-CDSMs and UC-FBSMs (UC-HYB-MMC) is presented to further enlarge the adjustable range of dc voltage. Detailed comparisons indicate that the UC-CD- and UC-HYB-MMCs can reduce the valve costs by 32% and 25%, respectively, and volumes by 39% and 34%, respectively, compared with HB-MMCs. Simulation and experimental results verify the steady-state and dc-fault clearance of the proposed topologies, and that the capacitor voltages in the UC-FBSMs and UC-CDSMs are well maintained and balanced in the UC-HYB-MMC.

Modular Multilevel Converter (MMC) has been widely used in medium/high voltage direct current transmission, motor drive, and renewable energy power generation, etc. The reliability requirements of MMC system which is composed of sub-modules(SM) as building blocks, are getting crucial. However, the testing for reliability of SMs in a full MMC system is time consuming and costly. In this paper, a mission profile emulator for SMs in MMC system is therefore focused, by using this mission profile emulator, the SMs can be tested individually without building a full MMC system. Simulation results show that the mission profiles of the SM under test is well agrees with the SM in a complete MMC system.

The thermal management plays an important role in improving the reliability and lifetime of high power converters, especially for the high voltage direct current (HVdc) transmission system. In the voltage source converter based HVdc systems (VSC-HVdc), the hybrid modular multilevel converters (MMCs) are taken as the excellent candidates due to their dc short-circuit fault ride-through ability and less submodule (SM) devices. Furthermore, the voltage modulation index of hybrid MMCs can be promoted to achieve higher power rating and efficiency. However, in this article, it is revealed that thermal stress distribution inside the SMs becomes more unbalanced under a high voltage modulation index, which would lead to serious thermal fatigue. To overcome this problem, the active bypass with thyristor for half-bridge submodules (HBSMs) and symmetrical modulation for full-bridge submodules (FBSMs) based active thermal control strategies are employed. With the presented thermal control strategies, the junction temperature of the most stressed devices in both HBSMs and FBSMs is reduced enormously. Besides, the thermal control strategy does not bring negative influence on the steady-state output performance of hybrid MMC. Finally, the theoretical analysis and effectiveness of the proposed control methods are verified based on a laboratorial MMC prototype.

A large high-voltage direct current (HVdc) reactor is required in modular multilevel converter (MMC) projects to realize dc fault current limiting (FCL). This condition may result in adverse effects on MMC control dynamics and oscillation and instability of HVdc systems. In this article, a virtual reactor (VR) control strategy is proposed to reduce a fixed large HVdc reactor. The VR characteristic of MMCs is revealed and analyzed as a controlled reactor, and the inductance of this reactor can be directly controlled by the discharge degree of submodule capacitors. A virtual reactor fault current limiting (VRFCL) control strategy in which VR can effectively limit dc fault current and substitute the fixed HVdc reactor is proposed accordingly. Simulation and experimental results verify the proposed control strategy. The adoption of the proposed strategy can eliminate the undesirable effect caused by an HVdc reactor, and the sub-module (SM) capacitor voltage can be reserved well. In addition, fault clearance time and fault energy dissipation can be reduced. The proposed VRFCL control is beneficial for MMCs to safely ride through dc fault in a continuous operation manner.

This article proposes a methodology of Cost-Performance Assessment (CPA) enabling the efficient cost evaluation required for the Cost-Benefit Analysis (CBA). The proposed method is applied for the Modular Multilevel Converter (MMC) in offshore wind high voltage direct current (HVDC) transmission. Thanks to the developed model, an analysis of submodule voltage rating is performed demonstrating the interest of this methodology in the evaluation of new technologies for HVDC transmission. The analysis shows that increasing the submodule (SM) voltage could lead to savings in the MMC cost and weight.

(English) Dynamic behavior of modern power system is increasingly influenced by the dynamics of power converters. At the generation level, a high volume of wind and solar energy with their large-scale power converters are replacing conventional synchronous generators. At the transmission level, many High Voltage Direct Current (HVDC) projects based on Modular Multilevel Converter (MMC) technology are commissioned to transfer offshore wind to the load centers, interconnect two non-synchronous AC grids, or two different nodes of the same AC grid (as an embedded link) to enhance the security of supply. The consumption level also faces such high integration of power converters since the modern flexible loads, such as electric vehicles, industrial motor drives, and recent hydrogen electrolyzers, are connected to the power system via power converters. Such transformation in generation, transmission, and consumption levels leads to the power dynamics that have never been experienced before in the conventional power systems. The high penetration of power converters may cause several challenges: reduction in the system total inertia and short-circuit current, excitation of undesirable interactions among control loops, reduction in stability margin, and loss of devices in the context of fault-ride through (FRT). Such challenges can be addressed by appropriate adjustments in the control systems of power converters. At the transmission level, this thesis focuses on improving the dynamic behavior of HVDC systems. A methodology is suggested to study the small-signal stability and evaluate potential interactions that may happen among control loops of two HVDC converter stations. Next, a multivariable controller based on H-inf design practice is developed to optimize the dynamic behavior of the system. As a follow-up study, mu-synthesis control approach is adopted to make HVDC control resilient against AC grid impedance variation. In the context of FRT performance, the fault operation of the HVDC system is improved by appropriate modification of the MMC control loops. Finally, a brief study on the DC voltage droop control design is conducted on a multi-terminal HVDC system. At the generation level, this thesis investigates the dynamic behavior of grid-forming control during fault events in a low-strength power system. It investigates the complication related to the existing grid codes and suggests two FRT controls for AC voltage support during fault recovery. As the last step, this thesis evaluates the feasibility of modern flexible loads to provide grid-forming services to the low-strength power grid. A hydrogen electrolyzer is used as an example and the operational constraints related to the hydrogen production are linked to the grid-forming functionalities. (Català) El comportament dinàmic del sistema de potència modern està cada vegada més influenciat per la dinàmica dels convertidors de potència. A nivell de generació, un gran volum d'energia eòlica i solar amb els seus convertidors de potència a gran escala està substituint els generadors síncrons convencionals. A nivell de transmissió, molts projectes de corrent continu d'alta tensió (HVDC) basats en la tecnologia Modular Multilevel Converter (MMC) s'encarreguen de transferir l'eòlica marina als centres de càrrega o interconnectar dues xarxes de CA per millorar la seguretat del subministrament. El nivell de consum també s'enfronta a una integració tan alta dels convertidors de potència, ja que les càrregues flexibles modernes, com ara vehicles elèctrics, accionaments de motors industrials i electrolitzadors d'hidrogen recents, es connecten al sistema elèctric mitjançant convertidors de potència. Aquesta transformació en els nivells de generació, transmissió i consum condueix a una dinàmica de potència que mai s'havia experimentat abans en els sistemes de potència convencionals. L'elevada penetració dels convertidors de potència pot provocar diversos reptes: reducció de la inèrcia total del sistema i de la potència de curtcircuit, excitació d'interaccions indesitjables entre llaços de control, reducció del marge d'estabilitat i pèrdua de dispositius en el context de fallada (FRT). Aquests reptes es poden abordar mitjançant ajustos adequats en els sistemes de control dels convertidors de potència. A nivell de transmissió, aquesta tesi se centra en la millora del comportament dinàmic dels sistemes HVDC. Es proposa una metodologia per estudiar l'estabilitat del senyal petit i avaluar les interaccions potencials que poden passar entre els bucles de control de dues estacions convertidores HVDC. A continuació, es desenvolupa un controlador multivariable basat en la pràctica de disseny H-inf per optimitzar el comportament dinàmic del sistema. Com a estudi de seguiment, s'adopta un enfocament de control de sintetització-mu per fer que el control HVDC sigui resistent a les variacions en la impedància de la xarxa de CA. En el context del rendiment FRT, el funcionament de falla del sistema HVDC es millora mitjançant les modificacions adequades als bucles de control MMC. Finalment, es realitza un breu estudi sobre el disseny de control de caiguda de tensió de CC en un sistema HVDC multiterminal. A nivell de generació, aquesta tesi investiga el comportament dinàmic del control de formació de xarxa durant esdeveniments de falla en un sistema d'energia de baixa inèrcia. Investiga la complicació relacionada amb els codis de xarxa existents i suggereix dos controls FRT per al suport de la tensió de CA durant la recuperació de fallades. Com a darrer pas, aquesta tesi avalua la viabilitat de càrregues flexibles modernes per proporcionar serveis de formació de xarxa a la xarxa elèctrica de baixa resistència. Com a exemple s'utilitza un electrolitzador d'hidrogen i les limitacions operatives relacionades amb la producció d'hidrogen estan vinculades a les funcionalitats de formació de la xarxa. (Español) El comportamiento dinámico de los sistemas eléctricos modernos está cada vez más influido por la dinámica de los convertidores de potencia. A nivel de generación, un gran volumen de energía eólica y solar con sus convertidores de potencia a gran escala están sustituyendo a los generadores síncronos convencionales. A nivel de transmisión, se están encargando muchos proyectos de corriente continua de alta tensión (HVDC) basados en la tecnología de convertidores multinivel modulares (MMC) para transferir la energía eólica marina a los centros de carga, interconectar dos redes de CA no síncronas o dos nodos diferentes de la misma red de CA (como enlace integrado) para mejorar la seguridad del suministro. El nivel de consumo también se enfrenta a una integración tan elevada de los convertidores de potencia, ya que las cargas flexibles modernas, como los vehículos eléctricos, los accionamientos de motores industriales y los recientes electrolizadores de hidrógeno, se conectan al sistema eléctrico a través de convertidores de potencia. Esta transformación en los niveles de generación, transmisión y consumo da lugar a una dinámica de potencia nunca antes experimentada en los sistemas eléctricos convencionales. La alta penetración de los convertidores de potencia puede causar varios retos: reducción de la inercia total del sistema y de la corriente de cortocircuito, excitación de interacciones indeseables entre los bucles de control, reducción del margen de estabilidad y pérdida de dispositivos en el contexto de la conmutación por fallo (FRT). Estos retos pueden abordarse mediante ajustes adecuados en los sistemas de control de los convertidores de potencia. A nivel de transmisión, esta tesis se centra en mejorar el comportamiento dinámico de los sistemas HVDC. Se propone una metodología para estudiar la estabilidad de pequeña señal y evaluar las posibles interacciones que pueden producirse entre los lazos de control de dos estaciones convertidoras HVDC. A continuación, se desarrolla un controlador multivariable basado en la práctica de diseño H-inf para optimizar el comportamiento dinámico del sistema. Como estudio complementario, se adopta un enfoque de control mu-síntesis para que el control HVDC sea resistente a la variación de la impedancia de la red de CA. En el contexto del rendimiento FRT, se mejora el funcionamiento en fallo del sistema HVDC mediante la modificación adecuada de los bucles de control MMC. Por último, se realiza un breve estudio sobre el diseño del control de droop de tensión de CC en un sistema HVDC multiterminal. A nivel de generación, esta tesis investiga el comportamiento dinámico del control de formación de red durante eventos de fallo en un sistema eléctrico de baja tensión. Investiga la complicación relacionada con los códigos de red existentes y sugiere dos controles FRT para el soporte de tensión de CA durante la recuperación de fallos. Como último paso, esta tesis evalúa la viabilidad de las cargas flexibles modernas para proporcionar servicios de formación de red a la red eléctrica de baja potencia. Se utiliza como ejemplo un electrolizador de hidrógeno y se relacionan las restricciones operativas relacionadas con la producción de hidrógeno con las funcionalidades de formación de red.

This paper proposes a new strategy for balancing the Capacitor Voltages (CVs) for Modular Multilevel Converters (MMCs). The balancing is one of the main challenges in MMC applications and it is usually solved by adopting a global arm control approach. For performing such an approach, a sorted list of the SubModules (SMs) according to their capacitor voltages is required. A common way to accomplish this task is to implement a sorting algorithm in the same controller used for the modulation technique. However, the execution time and the computational efforts of these kinds of algorithms increase very rapidly when the number of SMs grows. A novel idea is presented in this paper by using a mapping strategy that directly stores in a ranked list the SMs according to the measured CVs. Avoiding the use of sorting algorithms leads to a considerable reduction of the execution time as well as the computational efforts.

Modulation strategy plays an important role in the good performance of modular multilevel converter (MMC). Since MMC has a special structure as well as a large number of submodules (SMs), it is almost impossible to apply the conventional multilevel space vector modulation (SVM) algorithm in it. In this study, a simplified SVM implementation method is proposed by grouping SMs. With the presented method, the high‐level SVM process for MMC can be easily done by implementing multiple two‐level or three‐level SVM algorithm, while the complicated offline or online efforts/tasks about mapping switching states or sequences in the conventional multilevel SVM are not necessary any more. In order to improve the harmonic characteristics, the sampling time of different subunits (SUs), each of which is formed by grouping a few SMs, is staggered evenly, which helps to achieve a higher equivalent switching frequency and less low‐order harmonics. Further, the capacitor voltage balance of SMs is improved by rotation strategies between SUs or inside each SU even without any capacitor voltage detecting or sorting. Since the presented method is independent of the number of SMs, it can be very easily expanded into a high‐level MMC. These propositions are verified by experiment.