A structure of millimeter-wave on-chip transmission line using redistributed copper wire and ground shield

We present a general modeling methodology for metal fill parasitic capacitance in on-chip transmission lines. Our approach is based on reducing the problem complexity in all three dimensions. Typical speed-up is 16 fold. The maximum error in self and mutual capacitance is < 6 % and < 10 %, respectively over a wide range of parameters. The agreement with measurements is within 2.1 %. We predict the slow-wave factor of transmission line designs with < 1.2 % error and Q degradation with < 4 % error.

Microwave and Optical Technology LettersVolume 5, Issue 9 p. 476-476 Article Second comment on “the recurrence matrix technique for the arbitrary millimeterwave and microwave planar transmission lines” R. Pregla, R. PreglaSearch for more papers by this authorW. Pascher, W. PascherSearch for more papers by this author R. Pregla, R. PreglaSearch for more papers by this authorW. Pascher, W. PascherSearch for more papers by this author First published: August 1992 https://doi.org/10.1002/mop.4650050921AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat No abstract is available for this article. Volume5, Issue9August 1992Pages 476-476 RelatedInformation

We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- μm CMOS process with a 500- μm long PFL, post-layout simulations show that pulses of 10.4-ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4-mm-long PFL is implemented in the commercial 0.13- μm technology. Pulses of ~116-ps duration and 205-300-mV amplitude on a 50-Ω load are obtained when the power supply is tuned from 1.2 to 1.6 V. Measurement connection setup is the main reason for the discrepancies among measurements, modeling, and simulation analyses.

This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific pattern. Based on this process, a volume is introduced underneath the front side structure and the lossy LRSi substrate is replaced by air, which is the ideal substrate with no loss. Using this method, the substrate loss that contributes the majority part of total loss in mm-wave circuits on LRSi is eliminated. As the operating frequency goes into mm-wave region, the circuit size is scaled down so that the suspended portion is so small that it will not increase the mechanical instability of the structure. Therefore, the proposed suspended membrane on LRSi technology provides an excellent platform to construct mm-wave components. A U-shaped slotline resonator formed on the first redistribution layer is proposed and its quality factors are studied in detail. A second-order bandpass filter is designed and implemented by cascading two such U-shape slotline resonators. The measured frequency responses exhibit good filtering performance, with fractional bandwidth of 13.9% at 126.8 GHz, midband insertion loss of 3.9 dB and passband return loss larger than 14.2 dB. It demonstrates that the proposed suspended membrane on LRSi technology is an excellent candidate for designing low loss mm-wave components.

Development of an electron cyclotron equatorial launcher has proceeded with a series of prototype tests and design enhancements intended to improve reliability and functionality of the launcher. The design enhancements include adaptation of the launcher steering angles such that one of three beam rows of the launcher is necessarily flipped to perform counter current drive to conform to a new ITER physics requirement. Also, the top and bottom steering rows have been tilted at an angle of 5 deg so that the top and bottom beam rows can be accessed from on-axis to near midradius. Furthermore, the position of the fixed focusing mirror that forms a quasi-optical in-vessel millimeter-wave (mm-wave) transmission line is modified to increase the nuclear shielding capability. A high-power experiment of the mm-wave launching system mock-up fabricated based on the design confirmed a successful steering capability of 20 to 40 deg. It was measured that some stray radio-frequency power propagated in the beam duct and generated some heat on the duct. Prototype tests also include the fabrication of the blanket shield module and partial port plug mock-up and have shown no serious technological issue regarding the fabrication and cooling functionality.

A causal and compact fractional-order model is developed for complementary metal-oxide-semiconductor (CMOS) on-chip transmission line (T-line) at Terahertz (THz) frequencies. With consideration of the loss from frequency-dependent dispersion and nonquasi-static effects at THz, good agreement of characteristic impedance is observed between the proposed fractional-order model and the measurement up to 110 GHz, while traditional integer-order model can only match up to 10 GHz. The developed fractional-order model is further deployed in the design and analysis of CMOS-based THz integrated circuits that utilize T-line, such as standing-wave oscillator, which has significantly improved accuracy with causality.

To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is proposed and optimized. We propose a signaling structure to compensate the distortion and attenuation of on-chip transmission lines, which uses passive compensation and inserts repeated transceivers composing sense amplifiers and inverter chains. An optimization flow for designing this scheme based on eye-diagram prediction and sequential quadratic programming (SQP) is devised. This flow is used to study the latency, power dissipation and throughput performance of the new global wiring scheme as the technology scales from 90 nm to 22 nm. Comparing to repeated RC wire, experimental results demonstrate that at 22 nm technology node, the new scheme can reduce the normalized delay by 80%-95%, the normalized energy consumption by 50%-94%. The normalized latency is 10 ps/mm, the energy per bit is 20 pJ/m, and the throughput is 15 Gbps/mum. All performance metrics are scalable with technology, which makes this approach a potential candidate to break the "interconnect wall" of digital system performance.

This article proposes an LC-based spiral transmission line structure, which can effectively reduce the area of ON-chip transmission lines. The quarter-wavelength transmission line realized by this transmission line structure can be widely used in millimeter-wave circuits design. Based on the LC-based spiral transmission line structure, a 28-GHz single-pole double-throw (SPDT) switch and a 37-GHz Wilkinson power combiner are implemented with an area of only 0.028 mm² in 65-nm CMOS. Measurement results indicate that the SPDT switch has an insertion loss of less than 1.5 dB and an isolation better than 23.7 dB in the frequency range from 20 to 35 GHz. The insertion loss and the isolation of the Wilkinson power combiner at 36.9 GHz is 0.9 and 30.3 dB, respectively. IEEE

On-chip microstrip and coplanar waveguide structures were designed and fabricated in RF CMOS foundry processes. The wideband transmission line characteristics such as characteristic impedance, attenuation constant, propagation delay, and their electrical RLC parameters were evaluated based on S-parameter measurements in the millimeter-wave range. In addition, a SPICE-compatible RLC lumped element model including the skin-effect and the substrate RC network is employed to account for transmission line effects in interconnect over a wide frequency range up to 110 GHz.

A technique is described for determining the 'transmission line' voltage in the moment method field solution for different transmission line structures. An integral equation is developed which uses the full wave current distribution to find the voltage at arbitrary points along the transmission line. The technique is useful for reducing errors in port-to-port impedance calculations by moving the terminal plane away from the fringe fields caused by the introduction of a source. >

Composite right/left-handed (CRLH) transmission line structures based on the folded substrate integrated waveguide (FSIW) are presented and discussed in this paper. This FSIW-based CRLH (FSIW-CRLH) transmission line exhibits much lower cut-off frequencies as compared to the ordinary FSIW of the same footprint, and furthermore, it requires only one-half width of the conventional substrate integrated waveguide (SIW) based CRLH (SIW-CRLH) transmission lines while possessing the same dispersion characteristics. In addition, the proposed structure offers the advantage of a high quality factor for preventing the guided-wave circuits from radiation as suffered in the previous open CRLH transmission line structures when operated in the fast-wave region. All of the aforementioned properties lend the proposed FSIW-based CRLH transmission lines best suited to miniaturized and guided-wave microwave applications. In this paper, a comprehensive study on the FSIW-CRLH transmission structures is conducted by means of its dispersion relation and Bloch impedance. In addition, two partial <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> -plane filters are implemented here to demonstrate the capabilities of miniaturization and high quality factor based on the proposed FSIW-CRLH structures. The resultant filters are shown to have about 80% size reduction as compared to the conventional FSIW filters, and 59% size reduction as compared to the SIW-CRLH filters. To the best of our knowledge, it is the first time that the partial <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> -plane filters are implemented utilizing both the dispersion behavior of the CRLH transmission structures and the structural benefits of the FSIW configuration.

This paper discusses radiation loss of on-chip transmission-line. Since terahertz applications of integrated circuits are emerging, precise modeling in terahertz region is needed. We evaluate conductor loss, dielectric loss and radiation loss of on-chip transmission-line by a full-wave field solver. Simulation results show that design focusing conductor loss may cause large radiation loss in terahertz region. Quantitative evaluation of the impact of radiation loss is demonstrated. Also we show that thick signal wire and differential line is effective to reduce the loss.

In radio frequency (RF) circuits the lumped model assumptions are often not valid anymore. To circumvent this problem, mixed-level circuit/electro-magnetic/device simulation allows the use of Maxwell's and semiconductor equations for the critical devices and lumped models for the ambient circuitry. Besides AC, DC, periodic steady state and transient analysis, the multirate partial differential equation technique is employed for RF circuitry, based on a spline/wavelet expansion of the waveforms. The novel technique is demonstrated for RF circuits with on-chip inductors, transmission lines and baluns, modeled as 3D devices.

Transmission system operators have to utilize their network grids to a maximum degree of transmission capability. Increased current in the transmission lines especially in close proximity to metallic pipelines will cause an electromagnetic interface between high voltage transmission lines and neighbouring buried pipes, which may limit the maximum transmission capability of the transmission lines. Especially in Germany, this is a big challenge due to the dense infrastructure and population. Implementing a compensation line under ground or on tower combined with transmission line structures may reduce the total induced electromotive force (EMF), which induces a voltage to the pipeline. However, the compensation line is not always effective, as it may increase the produced magnetic field and consequently induced EMF. The effectiveness of the compensation line depends on several parameters. In this paper, an analytical approach is developed to evaluate the effectiveness of the compensation line, reducing inductive coupling interface. A sensitivity analysis is carried out and discussed to find a better understanding of each concept of the compensation.

In this paper, a novel hollow substrate integrated waveguide (HSIW) is presented for realizing low-loss millimeter-wave (mm-wave) transmission lines embedded in multi-chip modules. A new analysis method for the HSIW is proposed by treating it as a combination of a two-dielectric loaded rectangular waveguide (RWG) and standard substrate integrated waveguide, where an effective dielectric constant, e e , is introduced. An HSIW prototype in the Ka-band is fabricated using a progressive-lamination low-temperature co-fired ceramic technique. The measured results agree well with theoretical calculations and simulations. An average of 0.009-dB/mm loss is achieved in Ka-band, which is comparable to an air-filled RWG. This shows that the technique has great potential for further development to realize highly integrated mm-wave modules.