A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform

In this brief, a new efficient radix-2 fast algorithm for the computation of type-III discrete Hartley transform of length that has a small arithmetic cost and is well suited for a very large-scale integration (VLSI) implementation is presented. This recursive method requires a small number of arithmetic operations compared with existing methods, has a regular and simple computational structure, and can be easily implemented. A small number of arithmetic operations are achieved with the proposed algorithm as compared with existing algorithms. Moreover, the regular and simple computational structure and the existing parallelism of the proposed algorithm offer the possibility of an efficient fast parallel VLSI implementation.

Based on the prime factor decomposition, this paper presents fast algorithms for type-III generalized discrete Hartley transform (GDHT). When N = p*q, where p and q are mutually prime, the length-N GDHT can be decomposed into p length-q type-III GDHT and q length-p type-III discrete cosine transform (DCT). The proposed algorithms achieve a substantial reduction of the number of additions and multiplications and possess a regular computational structure. In particular, a simple index mapping method is proposed to minimize the overall implementation complexity and cost.

This paper proposes a new VLSI algorithm for a prime length type II generalized discrete Hartley transform (DHT) that allows a high speed VLSI implementation and an efficient incorporation of the obfuscation technique with low overheads. The proposed algorithm is highly regular and modular, presents a low computational complexity, a high throughput and it can be efficiently mapped on linear systolic arrays. Using the obfuscation method, it presents the additional advantage of the hardware security. The proposed VLSI algorithm uses some regular and modular computational structures called quasi-band correlations and can be efficiently implemented on a VLSI chip using the systolic arrays architectural paradigm.

Reed-Solomon decoders can be designed using time or frequency domain algorithms. The main advantage of the time domain method is its regular computational structure, an attractive feature for a flexible VLSI implementation. The main disadvantage of this is the relatively high computation count, hence it is important to find means of reducing the computational complexity of the time domain method. Several modifications to the time domain Reed-Solomon decoding algorithm are described for reducing its computational complexity by about 60%, as well as regular VLSI architectures for implementing the time domain algorithm. The paper concludes with a discussion of the advantages and disadvantages of the time domain decoding technique.

This correspondence presents an odd-factor algorithm for the type-III discrete cosine transform (DCT) for uniform or mixed radix decomposition. By jointly using the old-factor and the existing radix-2 algorithms, a general decomposition method for arbitrarily composite sequence length is developed. A reduction of computational complexity can be achieved compared with that needed by other reported algorithms for M=2/sup m/. The decomposition approach has a simple computational structure and supports a wider range of choices for different sequence lengths.

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

Since the DCT performs very close to the statistically optimal Karhunen-Loeve transform (KLT), it is widely used in digital signal processing, especially for speech and image data compression. The DCT algorithms and VLSI architectures for real-time computation capabilities are required urgently. It is known that VLSI implementation of distributed arithmetic is very efficient for computing the convolution. An algorithm is presented to convert the DCT and inverse DCT (IDCT) to the skew-convolution. VLSI implementation of the algorithm has the same advantage as any implementation using distributed arithmetic.

The approximation method proposed in this paper converts each constant in a DCT algorithm into a minimum number of signed digits. Then any multiplication in the transform can be turned into a number of add-and-shift operations on an integer value. With this technique, any fast DCT algorithm can be made multiplierless. To reduce the algorithm complexity and the word length requirement, we developed an effective algorithm for converting any constant into a signed digits string with minimum number of non-zero signed digits and a reduced word length. The approximation errors of different constants could affect differently the MSE of the approximated algorithm. The simple strategy is to assign more digits to those constants whose errors are more sensitive to the MSE of the algorithm whose complexity will however increase when the total number of digits assigned to the constants becomes larger. This paper devised an efficient algorithm to find an optimized signed digits configuration for minimizing the MSE of the algorithm with a specified complexity. Experiment results show that Lee’s fast DCT algorithm approximated by the proposed method can be used to reconstruct images with high visual quality in terms of PSNR.

A new integer 4times4 transform is adopted in the new video coding standard H.264/AVC. To reduce the computation load of the new transform, the SSAVT model for 8times8 transform is applied into H.264 4times4 transform with some modifications. Then, three classes of pruned block are defined and the corresponding simplified butterfly computation processes are designed. Furthermore, a fast DCT algorithm is proposed, with which we can identify the class of pruned block, so as to adopt simplified computation, with the help of modified model for 4times4 transform. Simulation results show that the proposed DCT algorithm saves about average 55% computation of DCT compared with full computation

A new fast algorithm for computing prime-Length DCT through cyclic convolutions

In this paper we present a new VLSI algorithm for an efficient VLSI implementation of the Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithm decomposes the computation of the MDST into two modular and regular computational structures called pseudo-cycle convolution that have the same form. This can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array using interleaving. The obtained VLSI architecture has all the advantages of a pseudo-cycle convolution based systolic implementation, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology and low I/O cost. Moreover, a cost-effective application of an obfuscation technique can be achieved with low overheads.

This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology..

Parallel decision feedback decoding is the preferred algorithm for joint postcursor equalization and trellis decoding in 1000BASE-T Gigabit Ethernet, as it achieves most of the theoretically possible coding gain at a reasonable hardware complexity. However, the VLSI implementation of a 125 MHz, 14-tap parallel decision-feedback decoder (PDFD) is very challenging because of the critical path problem. This paper presents a pipelined 14-tap PDFD VLSI architecture for 1000BASE-T. The design is implemented in 3.3 V 0.16 /spl mu/m standard cell CMOS process and operates at 125 MHz to achieve 1 Gb/s throughput. Compared to a conventional 14-tap PDFD implementation, the processing speed is improved by a factor of two.

Discrete cosine transformation (DCT) is one of an efficient tool which facilitates compression of speech and image signals. This paper focuses on FPGA implementation of discrete cosine transform (DCT-II) which is valid for \( N = 2^{r} \), where N is the length of input sequence and \( r > 1 \). The architecture used is recursive in nature and implemented with reduced hardware complexity. The structure is designed using Verilog Hardware Description Language (HDL) and Zybo Zynq-7000 Development FPGA board is used for implementation. The design utilized \( 7.91\% \) LUTs, \( 6\% \) IOB, \( 32.5\% \) DSPs, and \( 1.43\% \) Flip flops and takes 26 clock cycles to compute all the output coefficients of DCT.

According to Wang, there are four different types of DCT (discrete cosine transform) and DST (discrete sine transform) and the computation of these sinusoidal transforms can be reduced to the computation of the type-IV DCT. As the algorithms involve different sizes of transforms at different stages they are not so regular in structure. Lee has developed a fast cosine transform (FCT) algorithm for DCT-III similar to the decimation-in-time (DIT) Cooley–Tukey fast Fourier transform (FFT) with a regular structure. A disadvantage of this algorithm is that it involves the division of the trigonometric coefficients and may be numerically unstable. Recently, Hou has developed an algorithm for DCT-II which is similar to a decimation-in-frequency (DIF) algorithm and is numerically stable. However, an index mapping is needed to transform the DCT to a phase-modulated discrete Fourier transform (DFT), which may not be performed in-place. In the paper, a variant of Hou's algorithm is presented which is both in-place and numerically stable. The method is then generalised to compute the entire class of discrete sinusoidal transforms. By making use of the DIT and DIF concepts and the orthogonal properties of the DCTs, it is shown that simple algebraic formulations of these algorithms can readily be obtained. The resulting algorithms are regular in structure and are more stable than and have fewer arithmetic operations than similar algorithms proposed by Yip and Rao. By means of the Kronecker matrix product representation, the 1-D algorithms introduced in the paper can readily be generalised to compute transforms of higher dimensions. These algorithms, which can be viewed as the vector-radix generalisation of the present algorithms, share the in-place and regular structure of their 1-D counterparts.