A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT

An efficient design approach for a systolic array VLSI implementation of a prime-length odd-squared generalized discrete Hartley transform is presented. It uses an appropriate hardware algorithm based on an efficient decomposition of the odd-squared GDHT into two circular correlation structures having the same form and length that can be computed in parallel. Using an appropriate hardware sharing technique results in high computing speed with low hardware complexity, together with all the other advantages of the systolic array implementation of circular correlation structures as low I/O cost, regular and modular structures and local connections.

This paper proposes a new VLSI algorithm for a prime length type II generalized discrete Hartley transform (DHT) that allows a high speed VLSI implementation and an efficient incorporation of the obfuscation technique with low overheads. The proposed algorithm is highly regular and modular, presents a low computational complexity, a high throughput and it can be efficiently mapped on linear systolic arrays. Using the obfuscation method, it presents the additional advantage of the hardware security. The proposed VLSI algorithm uses some regular and modular computational structures called quasi-band correlations and can be efficiently implemented on a VLSI chip using the systolic arrays architectural paradigm.

In this paper we present a new VLSI algorithm for an efficient VLSI implementation of the Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithm decomposes the computation of the MDST into two modular and regular computational structures called pseudo-cycle convolution that have the same form. This can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array using interleaving. The obtained VLSI architecture has all the advantages of a pseudo-cycle convolution based systolic implementation, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology and low I/O cost. Moreover, a cost-effective application of an obfuscation technique can be achieved with low overheads.

Consideration is given to the problem of mapping systolic array algorithms into efficient algorithms for a fixed-size hypercube architecture. The authors describe in detail several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to validate the technique experimentally, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MIMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings. >

The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more importantly, the topology of the interconnection network is not easy to implement in VLSI due to the so-called retrograde indexing. Due to this problem, there are few pipeline implementations for IDCT and DCT, although pipelining is an efficient engineering solution that allows high speed performance with a reduced hardware complexity and power consumption. In this paper, we present an efficient solution to successfully reformulate the IDCT algorithm with a focus on developing a modular and regular computation structure that can be easily implemented using a pipelined VLSI architecture. Using new restructuring input sequences that can be computed in parallel with the new SFG graph in a pipeline manner, a novel efficient fast algorithm for the computation of inverse discrete cosine transform is presented. The obtained SFG graph has the best structure that can be obtained for IDCT, avoiding the so-called retrograde indexing and being highly regular and modular. Moreover, the obtained SFG graph is scalable, being easy to extend to larger values of N that is a power of 2. It can also be used to obtain a generalization of a radix-2 algorithm for length $$N = p \cdot 2^{m}$$ , where “p” is a prime number. This algorithm is based on a recursive decomposition of the computation of the inverse DCT that requires a reduced number of arithmetic operations and has a regular and simple computational structure that can be easily implemented in VLSI in a pipeline manner. Its main advantages are its simple, regular and modular computational structure and its high potential to be pipelined so that it can be used to obtain an efficient pipeline VLSI implementation.

Due to the development of VSLI fabrication technologies systolic algorithms are now being implemented as practical hardware. As a result, it is becoming more important to know their design methodologies and the scope of their object problems. In this paper as a basis to know the scope of the object problems we formalize systolic algorithms as mathematical objects in a strict manner. In other words, it is formalized by a triple systolic array, a data location space, and a set of timing functions. Moreover, equivalence between systolic arrays is defined. Under this formulation we define a data dependency graph as a tool for analyzing the flow of information, and show that wiring structures can be classified into several types. We give a condition that it is reduced equivalently to a simple memory‐type one. Finally, we consider the data flow processed in a systolic array and give not only an equation for data flow, but also the initial arrangement for a necessary encounter for interaction between data flows.

Since neural networks (NNs) require an enormous amount of learning time, various kinds of dedicated parallel computers have been developed. In the paper a 2-D systolic array (SA) of dedicated processing elements (PEs) also called systolic cells (SCs) is presented as the heart of a multimodel neural-network accelerator. The instruction set of the SA allows the implementation of several neural algorithms, including error back propagation and a self organizing feature map algorithm. Several special architectural facilities are presented in the paper in order to improve the 2-D SA performance. A swapping mechanism of the weight matrix allows the implementation of NNs larger than 2-D SA. A systolically propagated instruction word accompanying each input vector inside the 2-D SA allows the operating mode to be changed progressively, avoiding intermediate inactive cycles inside the 2-D SA. An FPGA implementation of the proposed 2-D SA is presented.

In this paper, a new approach for the realization of 1D discrete cosine transform (1D-DCT) is presented. This approach is based on a new formulation of an odd prime-length DCT which uses two half-length cyclic convolutions with the same form which can be computed in parallel. Using this approach, a new efficient systolic array with outstanding performance in structural regularity, hardware cost of the PE's, average computation time, and I/O cost has been obtained, which is well suited for VLSI realization. The average computation time has been reduced to one half and the throughput has been doubled, as compared with a previous design. It possesses also a much lower control complexity, a simpler interconnection structure, and a simpler hardware structure of the PE's, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the systolic array previously proposed.

In this paper, we present a new systolic algorithm for an efficient design approach using a bi-port memory-based VLSI implementation of the DHT. Using auxiliary input and output sequences and appropriate permutations it is shown that it is possible to compute a prime-length DHT using two cyclic convolutions having the same form and length that can be computed in parallel leading to improve throughput with a reduced hardware and I/O costs. The two computation structures can be mapped on the same linear systolic array using an appropriate hardware-sharing technique. Adopting a bi-port memory-based systolic architecture we can further reduce the hardware complexity and I/O costs while preserving all the advantages of a cyclic convolution based systolic array implementation such as regularity, modularity and a good topology of the interconnection structure.

VLSI systolic arrays for band matrix multiplication

Design, VLSI implementation, and validation results of a patient-specific RBF-SVM algorithm for monitoring and closed-loop control of high blood pressure in patients with resistant hypertension are presented. To ensure minimal invasiveness, the algorithm only uses a single-channel ECG signal as its sensory input. The feature extraction and classification are designed and optimized to be inexpensive both in terms of computational resources and energy consumption, enabling algorithm's integration within the highly-restricted size and power budget of an implantable device. The VLSI implementation using a hardware description language is also presented. Our results show that the implementation of the algorithm on a miniature Microsemi AGL250 low-power FPGA requires 493 logic elements, 7.4kbit of memory, consumes 19.98μW dynamic power (clocked at 1MHz), and yields a classification latency of 180μs. The algorithm classification performance is evaluated on a two different pre-recorded labeled ECG database with 14 healthy and 14 sick subjects and shows an average sensitivity, specificity, and accuracy of 89%, 98%, and 94.5%, respectively.

This paper describes the implementation of the Pan-Reif iterative algorithm for matrix inversion on the re-usable systolic processor array for matrix multiplication. The calculation of initial approximations, matrix norms and matrix transposition are implemented on the same processor array. Further the inversion of several special matrices is also discussed. All phases of the iterative algorithm are integrated so that they can be executed without any communication with a host system. The parallel algorithms and the systolic designs were implemented using Occam.

The systematic design of full adder-based architectures for computing a 1-D circular convolution using the Residue Number System is introduced. The proposed architectures consist of three stages that exhibit regular and modular structure. Trade-offs between hardware complexity and speed are achieved by applying partitioning techniques to each stage. Through a recently developed multiplierless algorithm, the convolution is reduced to the computation of a series of squaring operations. Based on this fact, a general graph-based methodology for designing circuits that perform raising to the Nth power modulo m is presented. >

A new fast algorithm for computing prime-Length DCT through cyclic convolutions

Matrix and vector multiplications are widely used in signal processing in operations such as FIR and IIR filtering, feature extraction and classification. Frequently, signal processing must be done in real time requiring the use of special purpose VLSI hardware. Regular structures such as systolic arrays are well suited for matrix and vector operations and are also amenable to VLSI implementation. This paper describes efficient systolic arrays for matrix and vector multiplication, at both word and bit levels, and outlines three applications relevant for signal processing: a convolver, an IIR filter and a linear classifier.