An efficient systolic array algorithm for the VLSI implementation of the odd-squared generalized discrete Hartley transform

This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology..

This paper proposes a new VLSI algorithm for a prime length type II generalized discrete Hartley transform (DHT) that allows a high speed VLSI implementation and an efficient incorporation of the obfuscation technique with low overheads. The proposed algorithm is highly regular and modular, presents a low computational complexity, a high throughput and it can be efficiently mapped on linear systolic arrays. Using the obfuscation method, it presents the additional advantage of the hardware security. The proposed VLSI algorithm uses some regular and modular computational structures called quasi-band correlations and can be efficiently implemented on a VLSI chip using the systolic arrays architectural paradigm.

Exploiting data encoding and reordering for low-power streaming in systolic arrays

In this paper, a new approach for the realization of 1D discrete cosine transform (1D-DCT) is presented. This approach is based on a new formulation of an odd prime-length DCT which uses two half-length cyclic convolutions with the same form which can be computed in parallel. Using this approach, a new efficient systolic array with outstanding performance in structural regularity, hardware cost of the PE's, average computation time, and I/O cost has been obtained, which is well suited for VLSI realization. The average computation time has been reduced to one half and the throughput has been doubled, as compared with a previous design. It possesses also a much lower control complexity, a simpler interconnection structure, and a simpler hardware structure of the PE's, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the systolic array previously proposed.

Since neural networks (NNs) require an enormous amount of learning time, various kinds of dedicated parallel computers have been developed. In the paper a 2-D systolic array (SA) of dedicated processing elements (PEs) also called systolic cells (SCs) is presented as the heart of a multimodel neural-network accelerator. The instruction set of the SA allows the implementation of several neural algorithms, including error back propagation and a self organizing feature map algorithm. Several special architectural facilities are presented in the paper in order to improve the 2-D SA performance. A swapping mechanism of the weight matrix allows the implementation of NNs larger than 2-D SA. A systolically propagated instruction word accompanying each input vector inside the 2-D SA allows the operating mode to be changed progressively, avoiding intermediate inactive cycles inside the 2-D SA. An FPGA implementation of the proposed 2-D SA is presented.

In this paper we present a new VLSI algorithm for an efficient VLSI implementation of the Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithm decomposes the computation of the MDST into two modular and regular computational structures called pseudo-cycle convolution that have the same form. This can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array using interleaving. The obtained VLSI architecture has all the advantages of a pseudo-cycle convolution based systolic implementation, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology and low I/O cost. Moreover, a cost-effective application of an obfuscation technique can be achieved with low overheads.

This paper describes the implementation of the Pan-Reif iterative algorithm for matrix inversion on the re-usable systolic processor array for matrix multiplication. The calculation of initial approximations, matrix norms and matrix transposition are implemented on the same processor array. Further the inversion of several special matrices is also discussed. All phases of the iterative algorithm are integrated so that they can be executed without any communication with a host system. The parallel algorithms and the systolic designs were implemented using Occam.

In this paper a low complexity algorithm for the VLSI implementation of DST based on band-correlation structures is presented. The proposed algorithm presents a low arithmetic complexity and implicitly, a low hardware complexity. The computational structure is band-correlation type and the proposed computational structure present the advantage of low hardware and I/O costs with only four processing elements and a high-speed performance.

Discrete cosine transform (DCT) is widely used in signal processing. This paper presents a novel approach to perform DCT. DCT is expressed in terms of discrete moments via triangle function transforms and later Taylor series expansion. From this, a fast systolic array for computing moments is converted to compute DCT with only a few multiplications and without any cosine evaluations. The systolic array has advantages of pipelinability, regularity, modularity, local connectivity and scalability, thus making it to be very suitable for VLSI implementation. We provide an estimate of the realizability of our array in a 0.5 μm CMOS technology and comparisons with other methods. The execution time of the systolic array is only O(N \log_2 N/\log_2 \log_2N) in computing 1D N-point DCT if N is sufficiently large. The approach is also applicable to multiple dimensional DCT and DCT inverses.

VLSI systolic arrays for band matrix multiplication

This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs to be delivered at correspondingly high rates with a minimum delay. The proposed three-parallel RS decoder has been implemented 90 nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400 MHz and has a data throughput 9.6-Gbps. The proposed three-parallel RS decoder architecture has a much higher data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6 Gbps and beyond.

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-mum CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity

Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters. In this paper, a sampling rate converter is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. The proposed sampling rate converter requires lesser number of multipliers for implementation when compared with the sampling rate converters in the literature. A low pass filter having a single bandwidth sandwiched between two sampling rate converters can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two stage Frequency response masking approach (FRM) is used for the hardware efficient design of the original low pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed sampling rate converter. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a Software defined radio (SDR) channelizer is realized using the proposed design of continuously variable bandwidth filter.

Hybrid precoding is a cost-effective approach to support directional transmissions for millimeter-wave (mmWave) communications, but its precoder design is highly complicated. In this paper, we propose a new hybrid precoder implementation, namely the double phase shifter (DPS) implementation, which enables highly tractable hybrid precoder design. Efficient algorithms are then developed for two popular hybrid precoder structures, i.e., the fully- and partially-connected structures. For the fully-connected one, the RF-only pre-coding and hybrid precoding problems are formulated as a least absolute shrinkage and selection operator problem and a low-rank matrix approximation problem, respectively. In this way, computationally efficient algorithms are provided to approach the performance of the fully digital one with a small number of radio frequency (RF) chains. On the other hand, the hybrid precoder design in the partially-connected structure is identified as an eigenvalue problem. To enhance the performance of this cost-effective structure, dynamic mapping from RF chains to antennas is further proposed, for which a greedy algorithm and a modified K-means algorithm are developed. Simulation results demonstrate the performance gains of the proposed hybrid precoding algorithms over existing ones. It shows that, with the proposed DPS implementation, the fully-connected structure enjoys both satisfactory performance and low design complexity while the partially-connected one serves as an economic solution with low hardware complexity.

A new algorithm, Square-and-Multiply for Modular Exponentiation (SMME), is proposed to calculate a modular exponentiation that is the core arithmetic function in RSA cryptography. The SMME scans the exponent form its MSB and pre-computes a set of exponents to the maximum bit length of l. These pre-computed exponents are stored in a look-up table. By using the look-up table, the number of multiplications required for modular exponentiation can be reduced. Modular multiplications are performed using a modified Montgomery's algorithm. The SMME takes in the order of n<SUP>2</SUP>(1 + 1(2l)) cycles to execute one n-bit modular exponentiation. The memory size to accommodate the pre- computed exponents is a 2<SUP>l-1</SUP> (n + 1)-bit RAM. The SMME, with its regularity and local connections in a systolic array, makes it suitable for VLSI implementation. A 64-bit modular exponentiation chip is being designed using a 0.8 micrometers CMOS standard cell library from AMS. The simulation result show that at 25 MHz, the throughput is approximately 236 KBps; and an estimation of 40 KBps for a 512-bit exponent.