Systolic matrix and vector multiplication methods for signal processing

The systolic array implementation of artificial neural networks is one of the ideal solutions for communication problems generated by highly interconnected neurons. A systolic array is an arrangement of processors in an array where data flows synchronously across the array between neighbours, usually with different data flowing in different directions. The simulation of systolic array for matrix multiplication is the practical application in order to evaluate the performance of systolic array. In this paper, a two-dimensional orthogonal systolic array for matrix multiplication is presented. Perl scripting language is used to simulate a two-dimensional orthogonal systolic array compared to conventional matrix multiplication in terms of average execution time. The comparison is made using matrices of size 5xM versus Mx5 which M ranges from 1 to 10, 10 to 100 and 100 to 1000. The orthogonal systolic array results show better average execution time when M is more than 30 compared to conventional matrix multiplication when the size of the matrix multiplication is increased.

This book provides in relatively few pages an extensive tour of practical signal processing. It covers a lot of ground and works through multiple matrix mathematics and transformations. The text, developed from courses taught by Prof. Yao, includes seven opening chapters that provide background and supporting mathematics. With five chapters devoted to applications, the book has a nice balance for a course. The final four chapters are on systolic arrays, which are interesting but not essential to a course. The chapter on chaotic signal analysis and processing is another area that many people will find intriguing and useful. The practical side of this book and the attention to historical development help balance out all of the mathematics and make of the signal processing more memorable. There is also space devoted to the history of mathematical transforms and arrayprocessing systems. This book covers three basic areas: mathematics background, applications, and systolic arrays. Of the 16 chapters, nine are devoted to the mathematical foundations of signal processing, with four chapters on systolic arrays, as noted previously, as well as three on applications. But applications are also part of the mathematical background chapters, so this text is useful in a number of ways. Of course, the book covers the basics of Fourier transforms, autoregressive and moving average models, windows, wavelet transforms, and time–frequency representations. and Kalman filters. This is a compact book with broad coverage and an enjoyable read, making it a nice addition to a rather crowded shelf of books in this field.

The authors extend previous work concerning the development of novel spatial light modulators (SLMs)/charge-coupled devices detectors (CCDDs) based on optoelectronic architectures for performing high-speed numerical computing and signal processing. These architectures exploit the broadcast nature of light to achieve parallelism, thereby increasing throughput and reducing computing time. Architectures for performing basic vector and matrix multiplications are introduced. Various signal processing applications based on a simple SLM/CCDD-based device and its derivatives are also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Matrix multiplication (MM) is a basic operation for many Digital Signal Processing applications. A Systolic Array (SA) is often considered as one of the most favorable architecture to achieve high performance for matrix multiplication. In this paper, the design exploration for an approximate SA is pursued; three design schemes are proposed by introducing approximation in multiple sub-modules. An approximation factor $\alpha$ is introduced; it is related to the inexact columns in the SA to explore the accuracy-efficiency trade-off present in the proposed designs. In the evaluation, an 8-bit input operand matrix multiplication is considered; the Synopsys Design Compiler at 45nm technology node is used to establish hardware-related metrics. The Error Rate (ER), Normalized Mean Error Distance (NMED) and Mean Relative Error Distance (MRED) are used as figures of merit for error analysis. Results show that the proposed architecture for 8-bit matrix multiplication with an approximation factor $\alpha=7$ has the lower power consumption compared to existing inexact designs found in the technical literature with comparable NMED. In addition, a power delay product vs NMED analysis shows the proposed designs have a lower PDP so applicable to low power applications. The practicality of the proposed architecture is established by computing the Discrete Cosine Transform.

The design of optimal planar systolic arrays for matrix multiplication

VLSI systolic arrays for band matrix multiplication

Various artificial intelligence (AI) algorithms are proposed in recent years, the demand for computing complexity has also increased. Matrix multiplication is a computing unit commonly used in AI calculations. This paper proposes a novel sparse matrix multiplication optimized scalable systolic array multiplier, which has three characteristics compared to traditional matrix multipliers: 1. This paper deals with a sparse matrix multiplication optimization multiplier, which is achieved by the critical path. 2. This paper focuses on high-dimensional convolutional neural network computation and proposed a multiplier with an expandable feature, which can calculate the matrices that dimension below the multiplier itself. Compared with the inextensible multiplier, this improvement reduces power consumption when calculating low-dimensional data. 3. The matrix multiplier of the traditional systolic array has a pulsation relationship between columns, which introduced delay registers between adjacent columns. Therefore, we proposed a new structure based on the traditional systolic array which removes the delay module. We designed a 4*4 matrix multiplication and deployed it at the PYNQ-Z7020 field-programmable gate array (FPGA). The result shows that the proposed structure reduces the 9.2% calculation delay, saving 13.3% slice logic power consumption than the traditional multiplication.

The advantage of optical signal processing and computing is mainly due to its two-dimensional complex computing ability with the fastest speed. Of computation algorithms, quite a few are iterative or recursive, such as vector or matrix multiplication over a given matrix for many times, and the computation of derivatives of much high order, etc. These algorithms are also suitable for optical computing . To perform iterative algorithms, the output from a computation step reenters the system as the input for the next step, therefore a feedback loop is needed. Many optical signal processing systems have spatial light modulators that are electrically addressed, and the photon-to-electron and electron-to-photon conversions reduce the processing speed and increase the system complexity. In this paper we propose an all-optical signal processing system for performing the iterative algorithms by using a four wave mixing material which introduces a feedback loop in the system. We believe that this system may also be used as an optical two-dimensional dynamic memory device.

Bit-level systolic array circuit for matrix vector multiplication

This paper describes the implementation of the Pan-Reif iterative algorithm for matrix inversion on the re-usable systolic processor array for matrix multiplication. The calculation of initial approximations, matrix norms and matrix transposition are implemented on the same processor array. Further the inversion of several special matrices is also discussed. All phases of the iterative algorithm are integrated so that they can be executed without any communication with a host system. The parallel algorithms and the systolic designs were implemented using Occam.

In this paper, we present a general approach which specifically targets reduction of redundant computation in common digital-signal processing (DSP) tasks such as filtering and matrix multiplication. We show that such tasks can be expressed as multiplication of vectors by scalars and this allows fast multiplication by sharing computation. Vector scaling operation is decomposed to find the most effective precomputations which yield a fast multiplier implementation. Two decomposition approaches are presented, one based on a greedy decomposition and the other based on fixed-size lookup and this leads to two multiplier architectures for vector-scalar products. Analog simulation of an example multiplier shows a speed advantage by a factor of about 1.85 over a conventional carry save array multiplier. Further simulations using 0.18 /spl mu/ technology show up to 20% speed advantage over Booth encoded Wallace tree multipliers.

Publication in the conference proceedings of EUSIPCO, Rhodes, Greece, 1998

Fault-tolerant systolic arrays for matrix-vector multiplication are proposed. A novel method called the linear arithmetic code technique is introduced which can detect and correct n errors caused by a single faulty module in a linear systolic array. This approach can be extended to other matrix operations. >

Systolic arrays are widely used for high-performance digital computations, enabling efficient and parallel execution of operations such as matrix multiplication and convolution. They are deployed in digital signal processing and embedded systems, and they have been more recently adopted to accelerate deep neural networks. However, due to manufacturing defects, aging, and harsh environments, systolic arrays are vulnerable to faults, which can compromise computation reliability. These vulnerabilities call for reliability analysis and hardening methods. Since full triplication induces a high hardware overhead, this work introduces an automatic method that applies redundancy only to the most impactful flip-flops in the processing elements. FPGA simulations show a wide Pareto trade-off between reliability and hardware resources, offering flexible protection levels for fault-resilient systems.

Structure for FIR and IIR Filters