Performance Study of Two-Dimensional Orthogonal Systolic Array Matric Multiplication

The design of optimal planar systolic arrays for matrix multiplication

An even faster systolic array for matrix multiplication

Consideration is given to the problem of mapping systolic array algorithms into efficient algorithms for a fixed-size hypercube architecture. The authors describe in detail several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to validate the technique experimentally, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MIMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings. >

2D matrix multiplication on a 3D systolic array

Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware accelerators to effectively speed up the computation of matrix multiplication have been proposed, and several studies have attempted to design hardware accelerators to perform better matrix multiplications in terms of both speed and power consumption. Typically, accelerators with either a two-dimensional (2D) systolic array structure or a single instruction multiple data (SIMD) architecture are effective only when the input matrix has shapes that are close to or similar to a square. However, several CNN applications require multiplications of non-squared matrices with various shapes and dimensions, and such irregular shapes lead to poor utilization efficiency of the processing elements (PEs). This study proposes a configurable engine for neural network acceleration, called CONNA, whose computation engine can conduct matrix multiplications with highly utilized computing units, regardless of the access patterns, shapes, and dimensions of the input matrices by changing the shape of matrix multiplication conducted in the physical array. To verify the functionality of the CONNA accelerator, we implemented CONNA as an SoC platform that integrates a RISC-V MCU with CONNA on Xilinx VC707 FPGA. SqueezeNet on CONNA achieved an inference performance of 100 frames per second (FPS) with 2.36 mm2 and 83.55 mW in a 65 nm process, improving efficiency by up to 34.1 times better than existing accelerators in terms of FPS, silicon area, and power consumption.

The paper presents laboratory implementation of a photovoltaic artificial neural network (ANN) based maximum power tracking controller. The control purpose is to track the maximum available solar power in a photovoltaic array interfaced to an electric utility grid via a line-commutated inverter. The inverse dynamic characteristics of this scheme is identified by off-line training of a multilayer perceptron type neural network. The ANN output is used as the control signal to vary the line-commutated inverter firing angle, hence track the available maximum solar power. The weights of the ANN is updated by an online training algorithm which utilizes the online power mismatch error. This ensures online maximum solar power tracking. >

Architectures for the realization of block matching algorithms are discussed, with emphasis on highly concurrent systolic array processors. A mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of two-dimensional and one-dimensional systolic arrays are presented. The required transistor count and the maximum frame rate for real-time processing of video telephone and TV signals using currently available CMOS technology are estimated. >

Based on discussions of the hardware implementations of artificial neural network (ANN), the single layer architecture to FPGA of the back propagation artificial neural network (BP ANN) is proposed. To construct the single layer architecture, the computing blocks of BP ANN are presented. The construction of the single layer architecture is described. According the experiments of the implementation in FPGA and the defects classification in ultrasonic non-destruction detection of carbon fibre reinforced plastic (CFRP), the single layer architecture of BP ANN performs well and can serve the applications.

In this paper a novel design of neural networks using 2-dimensional systolic array is proposed. Two techniques are applied in the design, namely, 2-dimensional pipelining and multirate processing (2 level clocking). 2-dimensional pipelining operation gives significant improvement in computation time compared to the currently known 1D and 2D systolic implementation schemes. Besides, multirate clocking is used so that weights (synapses) can be transmitted and passed systolically in a rate much higher than activation voltages, to achieve maximum array throughput and to eliminate global interconnections present in many array (including systolic) designs (thus reducing synchronization and propagation delay problems). This scheme of passing weights also saves area significantly since local storage area for the weights can be reduced. The design is applied to the implementation of a Hopfield neural net. >

This paper describes the implementation of the Pan-Reif iterative algorithm for matrix inversion on the re-usable systolic processor array for matrix multiplication. The calculation of initial approximations, matrix norms and matrix transposition are implemented on the same processor array. Further the inversion of several special matrices is also discussed. All phases of the iterative algorithm are integrated so that they can be executed without any communication with a host system. The parallel algorithms and the systolic designs were implemented using Occam.

A new two-dimensional systolic array for computing the discrete Fourier transform (DFT), with length N decomposable into the product of two relatively prime factors, 4M/sub 1/ and M/sub 2/, is presented. The architecture is constructed based on the row-column algorithm. It does not include any intermediate circuit for arranging data flow between the row-DFT and column-DFT modules. The system possesses the features of regularity and modularity, and is well suited to VLSI implementation. It has an efficiency of 100%, a throughput rate of one N-point transform per M/sub 2/ cycles, and an area*time/sup 2/ figure of AT/sup 2/=O((M/sub 1/+M/sub 2/)M/sub 2/N log/sub 2//sup 2/N), which is much smaller than the value of O(N/sup 3/ log/sub 2//sup 2/N) achieved by existing linear systolic array solutions. >

Various artificial intelligence (AI) algorithms are proposed in recent years, the demand for computing complexity has also increased. Matrix multiplication is a computing unit commonly used in AI calculations. This paper proposes a novel sparse matrix multiplication optimized scalable systolic array multiplier, which has three characteristics compared to traditional matrix multipliers: 1. This paper deals with a sparse matrix multiplication optimization multiplier, which is achieved by the critical path. 2. This paper focuses on high-dimensional convolutional neural network computation and proposed a multiplier with an expandable feature, which can calculate the matrices that dimension below the multiplier itself. Compared with the inextensible multiplier, this improvement reduces power consumption when calculating low-dimensional data. 3. The matrix multiplier of the traditional systolic array has a pulsation relationship between columns, which introduced delay registers between adjacent columns. Therefore, we proposed a new structure based on the traditional systolic array which removes the delay module. We designed a 4*4 matrix multiplication and deployed it at the PYNQ-Z7020 field-programmable gate array (FPGA). The result shows that the proposed structure reduces the 9.2% calculation delay, saving 13.3% slice logic power consumption than the traditional multiplication.

Matrix multiplication (MM) is a basic operation for many Digital Signal Processing applications. A Systolic Array (SA) is often considered as one of the most favorable architecture to achieve high performance for matrix multiplication. In this paper, the design exploration for an approximate SA is pursued; three design schemes are proposed by introducing approximation in multiple sub-modules. An approximation factor $\alpha$ is introduced; it is related to the inexact columns in the SA to explore the accuracy-efficiency trade-off present in the proposed designs. In the evaluation, an 8-bit input operand matrix multiplication is considered; the Synopsys Design Compiler at 45nm technology node is used to establish hardware-related metrics. The Error Rate (ER), Normalized Mean Error Distance (NMED) and Mean Relative Error Distance (MRED) are used as figures of merit for error analysis. Results show that the proposed architecture for 8-bit matrix multiplication with an approximation factor $\alpha=7$ has the lower power consumption compared to existing inexact designs found in the technical literature with comparable NMED. In addition, a power delay product vs NMED analysis shows the proposed designs have a lower PDP so applicable to low power applications. The practicality of the proposed architecture is established by computing the Discrete Cosine Transform.

Matrix and vector multiplications are widely used in signal processing in operations such as FIR and IIR filtering, feature extraction and classification. Frequently, signal processing must be done in real time requiring the use of special purpose VLSI hardware. Regular structures such as systolic arrays are well suited for matrix and vector operations and are also amenable to VLSI implementation. This paper describes efficient systolic arrays for matrix and vector multiplication, at both word and bit levels, and outlines three applications relevant for signal processing: a convolver, an IIR filter and a linear classifier.

A unique strategy for optimum multi-objective optimization for VLSI implementation of artificial neural network (ANN) is proposed. This strategy is efficient in terms of area, power, and speed, and it has a good degree of accuracy and dynamic range. The goal of this research is to find the sweet spot where area, speed, and power may all be optimised in a very large-scale integration (VLSI) implementation of a neural network (NN). The design should also allow for the dynamic reconfiguration of weight, and it should be very precise. The authors also use a 65-nm CMOS fabrication method to produce the circuits, and these results show that the suggested integral stochastic design may reduce energy consumption by up to 21% compared to the binary radix implementation, without sacrificing accuracy.