Systematic design of full adder-based architectures for convolution

Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

Elliptic Curve Cryptography operations rely heavily on the strong security of scalar multiplication. However, this operation is vulnerable to side channel (SCA) and fault injection (FA) attacks. The use of alternative arithmetic systems like Residue Number System (RNS) for all scalar multiplication underline operations has been proposed as an efficient countermeasure approach for the above attacks. In RNS, a number is represented as a set of smaller numbers, where each one is the result of the modular reduction with a given moduli basis. Under certain requirements, a number can be uniquely transformed from the integers to the RNS domain (and vice versa) and all arithmetic operations can be performed in RNS. This representation provides an inherent SCA and FA resistance to many attacks and can be further enhanced by additional RNS arithmetic manipulations or more traditional algorithmic countermeasures. In this paper, extending our previous work, we explore the potentials of RNS as an SCA and FA countermeasure. A description of RNS based SCA and FA resistance means is provided through appropriate scalar multiplication algorithmic variations, traces of the proposed algorithm are collected and the results are analyzed regarding the RNS countermeasure strength. More specifically, in this paper, a secure RNS based Montgomery Power Ladder based scalar multiplication algorithm is provided and is implemented on an ARM Cortex A7 processor. The implementation SCA-FA resistance is evaluated by collecting preliminary leakage trace results that validate our initial assumptions.

This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n −1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I & New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

Abstract—A new residue number system algebra has been previously proposed by the author. The algebra has solved an essential theoretical barrier in the residue number system and has enabled one to pursue additive operations in the residue number system to their full extent, overcoming such difficulties as restrictions on the sign or magnitude of numbers in the system. In this paper, basic theorems in the algebra are introduced first, and then, based on the theorems, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given. The theorems expound the behavior of a quantity treated as a veiled mysterious function in the literature. To the best knowledge of the author, hardware overflow-checking schemes and floatingpoint additive operations in the residue number system have never been reported elsewhere. So far, the upper limit of the magnitude of numbers in the system ever discussed has been the one that is theory-limited, and floating-point operations in the residue number system have never been discussed.

Fully Homomorphic Encryption (FHE) permits processing information in the form of ciphertexts without decryption. It can ensure the security of information in common technologies used today, such as cloud computing, the Internet of Things, and machine learning, among others. A primary disadvantage for its practical application is the low efficiency of sign and comparison operations. Several FHE schemes use the Residue Number System (RNS) to decrease the time complexity of these operations. Converting from the RNS to the positional number system and calculating the positional characteristic of a number are standard approaches for both operations in the RNS domain. In this paper, we propose a new method for comparing numbers and determining the sign of a number in RNS. We focus on the even ranges that are computationally simple due to their peculiarities. We compare the performance of several state-of-art algorithms based on an implementation in C++ and relatively simple moduli with a bit depth from 24 to 64 bits. The experimental analysis shows a better performance of our approach for all the test cases; it improves the sign detection between 1.93 and 15.3 times and the number comparison within 1.55–11.35 times with respect to all the methods and configurations.

Algorithms are developed to compute the number of active devices for residue number system (RNS) and binary number system (BNS) signal processing architectures. The precharged CMOS technology is used in order to build the filter architecture. The ROM lookup table and two's complement multiplier are used as the computational cells in the RNS and BNS, respectively. A direct implementation transversal systolic filter architecture is considered in RNS and BNS algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.

The scaling operation, i.e. the division by a constant factor followed by rounding, is a commonly used technique for reducing the dynamic range in digital signal processing (DSP) systems. Usually, the constant is a power of two, and the implementation of the scaling is reduced to a right shift. This basic operation is not easily implementable in the residue number system (RNS) due to its non positional nature. A number of different algorithms have been presented in the literature for the RNS scaling. In this paper, several RNS dynamic reduction techniques have been analyzed and the selected one is applied to a polyphase filter bank. A comparison of the filter bank scaled with RNS to binary and binary to RNS conversions, and the RNS scaled implementation is presented. A reduction of area and power consumption of about 30% for the scaling block is obtained.

In this work, we present the implementation of a finite impulse response (FIR) filter in the residue number system (RNS), in which we use a carry-save scheme in the binary representation of the residues to speed-up modular additions. We compare the carry-save RNS implementation with the implementations of the same filter in the traditional binary system and in plain RNS. Results show that the carry-save RNS filter is much faster and its energy dissipation per cycle comparable. Furthermore, we show that a multiple supply voltage approach for the plain RNS filter can lead to an additional reduction in power dissipation without performance degradation.

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).

Computer networks by providing data exchange capability between connected systems are driving a revolution in digital world. However, by improving the technology and producing low price devices, the number of connected devices is rapidly growing, and users are moving from one computer per person to multidevices per person including cell phones, home appliances, and wearable gadgets which are all connected to the internet. Therefore, new network concepts and also challenges have been introducing to overcome issues of rapid growth of the number of connected devices. Moreover, for future network with huge number of members more complex processors are needed to perform required process. Therefore, researchers of these fields should look for novel methods to overcome distinct emerging challenges. Recently, residue number system (RNS) as an alternative method to reduce network operations overhead attracts network researchers. The RNS has been used as a tool to reduce transmission energy and increase reliability in wireless sensor networks. Moreover, RNS can enhance switching process, and substitute lookup tables with simple modular operations in software-defined network. This chapter presents different types of RNS applications in computer networks in order to familiar researchers with these concepts.

Fast RNS (residue number system) algorithms which use only binary arithmetic are developed. Scaled residues, called pseudoresidues, are introduced by exploiting the cycle properties of each RNS channel and solving a Diophantine equation. Using the pseudoresidues instead of the original residue set to perform the desired computations, an RNS processor can be built with standard binary devices of small wordlength. The effectiveness of the procedure is shown by developing the pseudoresidue implementations of a modular multiplier for odd moduli RNS and of a FIR (finite impulse response) filter. The resulting structures exhibit complete reprogrammability for both moduli and coefficients, a very low number of fast machine cycles, and a square time-area product reduction. >

In the past, hardware realization of digital signal processing elements have been based upon binary arithmetic concepts. Because of the dependence between digits in binary arithmetic operations, the hardware required to construct arithmetic elements is cumbersome. In the residue number system, arithmetic operations can be performed with complete independence between digits and a corresponding reduction in hardware complexity. In fact, using current technology, arithmetic operations can be carried out using arrays of look-up tables placed in high density ROMs. This paper discusses the application of the residue number system to realizing digital signal processing elements using such arrays and advantages and disadvantages over conventional realizations are discussed. Examples are given of recursive filter and FFT butterfly element realization.

New efficient residue-to-weighted converters for multi-moduli residue number systems (RNS) based on sets {2/sup n1/-1, 2/sup n1/+1, 2/sup n2/-1, 2/sup n2/+1, ..., 2/sup nL/-1, 2/sup nL/+1} are presented. The moduli 2/sup n/-1 and 2/sup n/+1 are called conjugates of each other. The benefits offered by multi-moduli RNS processors relying on sets with pairs of conjugate moduli are: (1) large dynamic ranges, (2) fast and balanced RNS arithmetic, (3) simple and efficient RNS processing hardware, and (4) efficient weighted-to-RNS and RNS-to-weighted converters. The new converters presented in this paper are hardware-efficient since all the modulo adders required by them are adders mod(2/sup n/-1) which can easily be implemented as 1's complement adders. Furthermore, the largest such modulo adder is an adder modulo the square root of the system's dynamic range instead of modulo the entire dynamic range.