A Survey of Approximate Triple Modular Redundancy

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

With the development of satellite communications, on-board processing (OBP) obtains more and more attentions due to the increased efficiency and performance. However, the large amounts of digital circuits in the OBP transponders are sensitive to the high-energy particles in space radiation environments, which may cause various kinds of single event effect. Among these effects, single event upset (SEU) is the major potential reason for the instability of the satellite communication systems. Triple modular redundancy (TMR) is a classical and effective method for mitigating the SEU in digital circuits. However, since three identical logic modules and a voting circuit are needed in TMR, the overhead is so high that the scheme may not be applicable on the on-board digital processing platform with very limited area and power resources. Therefore, how to design a more cost-effective fault-tolerant method becomes a critical issue. Considering that FIR-like processing is frequently used on OBP platform, in this article, a dual modules (DM) plus checking module based on residue code (DM-CRC) architecture for SEU-tolerant FIR design is proposed. Although this architecture reduces the area overhead dramatically, we find that the fault missing rate is still high if single-sample checking (SSC) is used. To solve this problem, a Multi-sample checking DM-CRC (MSC-DM-CRC) is further proposed. Our analysis shows that the MSC-DM-CRC scheme can make the fault missing rate small enough without reducing the actual throughput. By simulations it is shown that, when the modulus for CRC is 7 and the number of samples for MSC is 4, the reduction of area overhead relative to TMR is over 20% and the fault missing rate is as low as 0.05%.

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

Space computing systems commonly use field-programmable gate arrays to provide fault tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level (RTL) code. Although effective, this approach has a 3× area overhead that can be prohibitive for many designs that often allocate resources before considering effects of redundancy. Although a designer could modify existing RTL code to reduce resource usage, such a process is time consuming and error prone. Integrating redundancy into high-level synthesis is a more attractive approach that enables synthesis to rapidly explore different tradeoffs at no cost to the designer. In this paper, we introduce a scheduling and binding heuristic for high-level synthesis that explores tradeoffs between resource usage, latency, and the amount of redundancy. In many cases, an application will not require 100% error correction, which enables significant flexibility for scheduling and binding to reduce resources. Even for applications that require 100% error correction, our heuristic is able to explore solutions that sacrifice latency for reduced resources, and typically save up to 47% when relaxing the latency up to 2×. When the error constraint is reduced to 70%, our heuristic achieves typical resource savings ranging from 18% to 49% when relaxing the latency up to 2×, with a maximum of 77%. Even when comparing with optimized RTL designs, our heuristic uses up to 61% fewer resources than TMR.

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness.

The challenging goal of designing interactive systems is to prevent faults caused by the control unit that could potentially lead to failures. When designing interactive systems, it is the behavior that is dominant in the process of modeling. Nevertheless, structural features in software application programming and their organization are seldom taken into account for test derivation. The consequence is a reduction in fault coverage with regard to find structural defects in such systems. This paper introduces an approach to reveal structural features of such systems that expose further test opportunities. The approach uses a graphical, event-based model of which structural features are extracted by simple transformations resulting into an increased fault coverage.

A highly reliable and low-overhead quadruple-node-upset tolerant latch design

The RISC-V architecture is increasingly deployed in safety-critical domains, such as automotive systems, yet the register file remains susceptible to Single Event Upsets (SEUs). Traditional fault-tolerance schemes like Triple Modular Redundancy (TMR) and Error Correction Codes (ECC) incur excessive area overhead (>200%) or significant performance penalties (15.3–20.5% timing degradation), and critically, cannot prevent error accumulation. To address this, we propose I-COR , an instruction-level correction scheme that targets register file data errors. When an instruction accesses a corrupted register, I-COR replaces it with a corrective instruction pair: the first instruction rectifies the erroneous value through the write-back path to prevent error accumulation, while the second re-executes the original operation. By reusing existing forwarding paths, this pair maintains pipeline efficiency, introducing just one-cycle correction latency. Implemented on the Ibex core and synthesized in 28 nm, 110 nm CMOS, and 180 nm SOI technologies, I-COR reduces area overhead by 50.92–62.83% compared to TMR while avoiding ECC’s timing degradation. Our automated two-stage fault-injection validation demonstrates I-COR’s effectiveness: it achieves complete elimination of critical faults (0% occurrence for both application output mismatches and system hangs) and reduces non-critical faults (internal architectural errors without system-level impact) down to 0.12–3.17%, outperforming existing schemes by 2.6–28.8×. By combining minimal area, zero timing penalty, single-cycle correction latency, and guaranteed prevention of error accumulation, I-COR provides an efficient architectural-level fault-tolerance solution specifically designed for register file protection in safety-critical three-stage pipeline RISC-V processors.

In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments demonstrate that the Message Passing Interface, the Arbiter and the Program Counters are the most vulnerable parts of the processor. Thus, these parts were selected as targets for the improvement. The fault tolerance method used for improving the Arbiter is based on using the Triple Modular Redundancy. As for the Message Passing Interface and the Program Counters the single bit error correction Hamming code is used. The experimental results show 11.8% improvement in error recovery and 15.1% reduction of failure rate at the cost of 1.01% area overhead.

Fault-tolerant designs for space applications on SRAM-based FPGAs typically require Distributed Triple Modular Redundancy (DTMR) or Block Triple Modular Redundancy (BTMR) to mitigate faults induced by ionizing radiation. These methods lead to a large area overhead, which, in turn, can make the design more susceptible to the radiation effects. The Reduced Precision Redundancy (RPR) technique has been proposed as a trade-off between area overhead and reliability. In this work, the RPR hardening technique is reviewed and compared to TMR by performing fault injection campaigns using a hardened Fast Fourier Transform (FFT) block as a case study. Results show that the implemented RPR not only saves FPGA resources, but also reduces the critical error rate and the impact of Common Mode Failures (CMF) with respect to the TMR solution.

Flexible router architecture for network-on-chip

The advent of in-memory computing has introduced a new paradigm of computation, which offers significant improvements in terms of latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect of the hardware variations and non-idealities of the emerging memory technologies may significantly compromise the accuracy of inferred neural networks and result in malfunctions in safety-critical applications. This article addresses the issue from three different perspectives. First, we describe the technology-related sources of these variations. Then, we propose an architectural-level mitigation strategy that involves the coordinated action of two checksum codes designed to detect and correct errors at runtime. Finally, we optimize the area and latency overhead of the proposed solution by using two accuracy-aware hardware-software co-design techniques. The results demonstrate higher efficiency in mitigating the accuracy degradation of multiple AI algorithms in the context of different technologies compared with state-of-the-art solutions and traditional techniques such as triple modular redundancy. Several configurations of our implementation recover more than 95% of the original accuracy with less than 40% of the area and less than 30% of latency overhead.This article is part of the themed issue 'Emerging technologies for future secure computing platforms'.

This work is concerned with the development of an algorithm for lowering the power consumption of the tester used in digital circuits with on-line testing (OLT) capability. The proposed scheme is generic and flexible in terms of tradeoffs regarding fault coverage and detection latency versus power and area overheads. Most of the works presented in the literature on OLT have emphasised on minimising area overhead and maintaining high fault coverage. However, power, which was mainly a concern for handheld devices, is now a first order impact factor for deep sub-micron designs. Its increased importance for OLT can be realised from the fact that the tester is executed concurrently with the circuit. The proposed technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for design of on-line fault detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal impact on performance in terms of coverage and latency, the proposed technique can lower the power and area consumption significantly, compared to traditional approaches.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.