Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

Using Bayesian networks in reliability evaluation for subsea blowout preventer control system

With the development of satellite communications, on-board processing (OBP) obtains more and more attentions due to the increased efficiency and performance. However, the large amounts of digital circuits in the OBP transponders are sensitive to the high-energy particles in space radiation environments, which may cause various kinds of single event effect. Among these effects, single event upset (SEU) is the major potential reason for the instability of the satellite communication systems. Triple modular redundancy (TMR) is a classical and effective method for mitigating the SEU in digital circuits. However, since three identical logic modules and a voting circuit are needed in TMR, the overhead is so high that the scheme may not be applicable on the on-board digital processing platform with very limited area and power resources. Therefore, how to design a more cost-effective fault-tolerant method becomes a critical issue. Considering that FIR-like processing is frequently used on OBP platform, in this article, a dual modules (DM) plus checking module based on residue code (DM-CRC) architecture for SEU-tolerant FIR design is proposed. Although this architecture reduces the area overhead dramatically, we find that the fault missing rate is still high if single-sample checking (SSC) is used. To solve this problem, a Multi-sample checking DM-CRC (MSC-DM-CRC) is further proposed. Our analysis shows that the MSC-DM-CRC scheme can make the fault missing rate small enough without reducing the actual throughput. By simulations it is shown that, when the modulus for CRC is 7 and the number of samples for MSC is 4, the reduction of area overhead relative to TMR is over 20% and the fault missing rate is as low as 0.05%.

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

The hunt for increased reliability in systems for critical applications is a never-ending process and is a point of concern for designers in several different fields, such as nuclear reactors. This concern becomes more prominent when a new device technology is integrated into the options for the development of those systems, such as programmable logic devices like the FPGA. With the constant breakthroughs in this technology, there has been an increase in the capacity and the performance of FPGAs. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. This work proposes a resilient and adaptable hardware architecture that increases the reliability of circuits implemented in FPGAs, based on a classic active redundancy model, Triple Modular Redundancy with spares. Also, it brings forth a novel hardware architecture that can easily be ported to different FPGA models without compromising performance, reliability, and availability. We discuss and analyze these requirements for the proposed architecture and show that it is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area.

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.

Space computing systems commonly use field-programmable gate arrays to provide fault tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level (RTL) code. Although effective, this approach has a 3× area overhead that can be prohibitive for many designs that often allocate resources before considering effects of redundancy. Although a designer could modify existing RTL code to reduce resource usage, such a process is time consuming and error prone. Integrating redundancy into high-level synthesis is a more attractive approach that enables synthesis to rapidly explore different tradeoffs at no cost to the designer. In this paper, we introduce a scheduling and binding heuristic for high-level synthesis that explores tradeoffs between resource usage, latency, and the amount of redundancy. In many cases, an application will not require 100% error correction, which enables significant flexibility for scheduling and binding to reduce resources. Even for applications that require 100% error correction, our heuristic is able to explore solutions that sacrifice latency for reduced resources, and typically save up to 47% when relaxing the latency up to 2×. When the error constraint is reduced to 70%, our heuristic achieves typical resource savings ranging from 18% to 49% when relaxing the latency up to 2×, with a maximum of 77%. Even when comparing with optimized RTL designs, our heuristic uses up to 61% fewer resources than TMR.

The advancement of semiconductor technology has driven the continuous reduction in transistor sizes, resulting in significant improvements in both area efficiency and power consumption. However, these advancements have also increased susceptibility to faults caused by energetic particles. Triple modular redundancy (TMR) is a well-known logical masking technique that employs three copies of a given circuit alongside majority voters, guaranteeing 100\% single-fault coverage in the replicated modules. This reliability, however, comes at the cost of over 200\% area overhead. The approximate TMR (ATMR) concept leverages non-exact module functionality to reduce the associated area overhead while accepting a reduction in fault coverage. This work provides a comprehensive survey of ATMR generation techniques, detailing the various approximation strategies and discussing the primary approximation control mechanisms. Additionally, it presents a comparative analysis of the surveyed works, focusing on scalability and the trade-offs between area overhead and fault coverage achieved by the generated ATMR designs.

In many applications such as critical life-saving systems, safety is an important design issue as well as reliability. Among various commonly-used approaches in the implementation of on-line unrepairable fault-tolerant systems, standby systems achieve the most satisfactory reliability figure, followed by duplex systems, hybrid systems and triple modular redundancy. Nevertheless, the safety figure of duplex systems is superior to that of the standby approach. In this paper, the failure rate of system modules and hard core is predicted by the M1L-HDBK-217E model, and we show that the reliability and safety figure of cold standby systems can be further dramatically improved by increasing the number of spare units. Furthermore, comparative measures such as the reliability improvement factor, the safety improvement factor and the mission time improvement factor are proposed for showing that long-term unmaintained systems have reliability and safety as high as other systems that must be repaired.

Energy-efficient triple modular redundancy scheduling on heterogeneous multi-core real-time systems

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

The RISC-V architecture is increasingly deployed in safety-critical domains, such as automotive systems, yet the register file remains susceptible to Single Event Upsets (SEUs). Traditional fault-tolerance schemes like Triple Modular Redundancy (TMR) and Error Correction Codes (ECC) incur excessive area overhead (>200%) or significant performance penalties (15.3–20.5% timing degradation), and critically, cannot prevent error accumulation. To address this, we propose I-COR , an instruction-level correction scheme that targets register file data errors. When an instruction accesses a corrupted register, I-COR replaces it with a corrective instruction pair: the first instruction rectifies the erroneous value through the write-back path to prevent error accumulation, while the second re-executes the original operation. By reusing existing forwarding paths, this pair maintains pipeline efficiency, introducing just one-cycle correction latency. Implemented on the Ibex core and synthesized in 28 nm, 110 nm CMOS, and 180 nm SOI technologies, I-COR reduces area overhead by 50.92–62.83% compared to TMR while avoiding ECC’s timing degradation. Our automated two-stage fault-injection validation demonstrates I-COR’s effectiveness: it achieves complete elimination of critical faults (0% occurrence for both application output mismatches and system hangs) and reduces non-critical faults (internal architectural errors without system-level impact) down to 0.12–3.17%, outperforming existing schemes by 2.6–28.8×. By combining minimal area, zero timing penalty, single-cycle correction latency, and guaranteed prevention of error accumulation, I-COR provides an efficient architectural-level fault-tolerance solution specifically designed for register file protection in safety-critical three-stage pipeline RISC-V processors.

In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments demonstrate that the Message Passing Interface, the Arbiter and the Program Counters are the most vulnerable parts of the processor. Thus, these parts were selected as targets for the improvement. The fault tolerance method used for improving the Arbiter is based on using the Triple Modular Redundancy. As for the Message Passing Interface and the Program Counters the single bit error correction Hamming code is used. The experimental results show 11.8% improvement in error recovery and 15.1% reduction of failure rate at the cost of 1.01% area overhead.

Fault-tolerant designs for space applications on SRAM-based FPGAs typically require Distributed Triple Modular Redundancy (DTMR) or Block Triple Modular Redundancy (BTMR) to mitigate faults induced by ionizing radiation. These methods lead to a large area overhead, which, in turn, can make the design more susceptible to the radiation effects. The Reduced Precision Redundancy (RPR) technique has been proposed as a trade-off between area overhead and reliability. In this work, the RPR hardening technique is reviewed and compared to TMR by performing fault injection campaigns using a hardened Fast Fourier Transform (FFT) block as a case study. Results show that the implemented RPR not only saves FPGA resources, but also reduces the critical error rate and the impact of Common Mode Failures (CMF) with respect to the TMR solution.

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead.