Enhanced concurrent error correcting arithmetic unit design using alternating logic

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation. © 2020 IEEE.

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

A vehicle accident report system was designed to detect accidents accurately and send message to related person. However, after accident, some components or modules can be damaged and it may cause failure of accident detection. Therefore, Triple Modular Redundancy (TMR) method was implemented in the system to mask faults within the modules and ensure the system to continue working. TMR is one of passive hardware redundancy methods. The system includes three MPU-6050 sensors functioning as vehicle tilt sensors to provide hardware redundancy, a TC9548A module serving as an I2C multiplexer, an Arduino Nano acting as a microcontroller and voter, and a NodeMCU ESP8266 responsible for transmitting message. Based on experiment results, the TMR system has a reliability value of 0.9928, a failure rate value of 0.0004/cycle, and accuracy of 3 sensor value of 85%. While, the non-redundancy system has a reliability value of 0.9286, a failure rate value of 0.0053/cycle, and accuracy of single sensor value of 57%. The results of the system process were sent to and displayed via an e-mail. It can be concluded that the TMR system has better performance than the non-redundancy one.

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

Nanoelectronic systems are now more and more prone to faults and defects, permanent or transient. Redundancy techniques are implemented widely to increase the reliability, especially the TMR - Triple Modular Redundancy. However, many researchers assume that the voter is perfect and this may not be true. This paper proposes a simple but effective fault-tolerant voter circuit which is more reliable and less expensive. Experimental results demonstrate its improvement over the former TMR structures.

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

Using Bayesian networks in reliability evaluation for subsea blowout preventer control system

International audience

Most of the applications require hard real time signal/data processing potentiality for which fast and dedicated VLSI architectures are the best solution. But designing such circuits lead to high occurrences of failure in the system. Hence there is a critical need for fault tolerance techniques for VLSI designs to increase the reliability of the system. Redundancy techniques are implemented widely to increase the reliability. By developing a fault tolerant system such as Triple Modular Redundancy (TMR), the FPGA can locate the errors and reconfigure the corrupted areas while maintaining the validity of system outputs. One of the drawbacks of this scheme is that the reliability of voter circuit is assumed to be perfect which may not be true. Hence, a novel fault-tolerant voter circuit (NFTVC) have been developed which is more reliable and leads to low power fault tolerant designs. Experimental results show that NFTVC is more reliable than the traditional TMR schemes. The hardware part of the design was done using Spartan-3 kit that is used for a rapid digital circuit. The system performance has been optimized using the Plan Ahead tool in Xilinx in order to reach and maintain the goals of the design. The implementation results provide a simultaneous improvement in power, delay and area.

A Triple Modular Redundant (TMR) system achieves high reliability by replicating data and all processing at three independent nodes. When TMR is used for database processing all nonfaulty computers must execute the same sequence of transactions, and this is ensured by a collection of processes known as schedulers . In this paper we study the implementation of efficient schedulers through analysis of various enhancements such as null transactions and message batching. The schedulers have been implemented in an experimental TMR system and the evaluation results are presented here.

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, quadruple time redundancy, is compared with a non-redundant adder, a triple modular redundancy adder, and a time shared triple modular redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with time shared triple modular redundancy to which it is most closely related, quadruple time redundancy results in a 40%-55% reduction in hardware complexity while incurring a reasonable delay increase.

Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption of a single circuit. In this work, we present a mathematical model that predicts the power consumption overhead based on the power characteristics of the basic module. We estimate power consumption in some case-study circuits protected by nMR in a commercial SRAM-based FPGA and compare to a proposed model that estimates power consumption penalty. Results demonstrate that nMR can be implemented with low power overhead in FPGAs and therefore it is a suitable technique for most applications synthesized into this type of programmable devices that need to cope with massive multiple faults.

Multiply–accumulate (MAC) units are essential components in Fast Fourier transform (FFT)-based digital signal processing (DSP) systems,wherein the efficient and accurate execution of large volumes of arithmetic operations is crucial. This paper presents a 32-bit fault-tolerant MAC architecture that integrates a radix -4 Modified Booth multiplier with a Triple Modular Redundancy (TMR)-based carry-look-ahead adder implemented using FPGA carry chain structures, which is capable of computing spectral correlation parameters from complex input signals. The proposed architecture processes the real and imaginary components of two complex signals and generates four spectral parameters: GAA,GBB,GABR, and GABI. The design was described using Verilog HDL and verified through functional simulations in the Xilinx Vivado design environment. Vivado synthesis and implementation reports showed efficient hardware utilization, successful timing closure, and an estimated on-chip power consumption of 0.39 W for the proposed architecture. The results indicate that the proposed architecture achieves accurate computation,high reliability, and efficient hardware utilization, which are suitable for real-time DSP systems.