Development of Fault Tolerant Digital System Using Triple Modular Redundancy

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.

A vehicle accident report system was designed to detect accidents accurately and send message to related person. However, after accident, some components or modules can be damaged and it may cause failure of accident detection. Therefore, Triple Modular Redundancy (TMR) method was implemented in the system to mask faults within the modules and ensure the system to continue working. TMR is one of passive hardware redundancy methods. The system includes three MPU-6050 sensors functioning as vehicle tilt sensors to provide hardware redundancy, a TC9548A module serving as an I2C multiplexer, an Arduino Nano acting as a microcontroller and voter, and a NodeMCU ESP8266 responsible for transmitting message. Based on experiment results, the TMR system has a reliability value of 0.9928, a failure rate value of 0.0004/cycle, and accuracy of 3 sensor value of 85%. While, the non-redundancy system has a reliability value of 0.9286, a failure rate value of 0.0053/cycle, and accuracy of single sensor value of 57%. The results of the system process were sent to and displayed via an e-mail. It can be concluded that the TMR system has better performance than the non-redundancy one.

Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation. © 2020 IEEE.

Scrubbing is an effective FPGA error detection and correction method for configuration memoryâǍŹs faults. Scrubbing, however, is a serial procedure with several milliseconds latency. This latency may allow some errors to affect the system functionality. To prevent this effect, we have devised our duplication method of reliability operating in parallel and hand-in-hand with scrubbing to recover from errors. Our experiments results demonstrate that mean time to failure (MTTF) is improved by 966% and 150% over the pure scrubbing and triple modular redundancy (TMR), respectively. Additionally, our method enters the safe fail procedure in the remaining cases.

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, quadruple time redundancy, is compared with a non-redundant adder, a triple modular redundancy adder, and a time shared triple modular redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with time shared triple modular redundancy to which it is most closely related, quadruple time redundancy results in a 40%-55% reduction in hardware complexity while incurring a reasonable delay increase.

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.

International audience

In digital systems design, the high-speed adders play an imperative role in modules like adders, multipliers, division, etc. to obtain the results quickly. In digital signal processor and computer data path circuits, carry look-ahead adder (CLA), carry save adder (CSA), carry select adder (CSeA) and carry skip adder are the mostly used fast adders to improve the performance of a system. This work mainly emphasizes on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of area. The popular methods like dual (DMR) and triple modular redundancy (TMR) are implemented to detect only but not correct an error and tolerate single event upset (SEU) error respectively. To tolerate multiple errors, for example, two, three and four errors, the 5-modular (quintuple), 7-modular (septuple), and 9-modular (nonuple) redundancy configurations are used respectively. For experimental results, the implementation of a simple addition of four 4-bit numbers is considered on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis software tool. Simulation results reveal that for example in nonuple MR, CSA using CSeA final stage obtain higher performance (45.7 MHz) with moderate power dissipation as 173.36 mW and at the cost of more LEs (216).

Increasing market pressure for industrial turbine controls that reduce cost of installation, increase availability, and reduce overall installation and commissioning time have driven systems in a new direction. This direction is away from complex and expensive triplex or TMR (Triple Modular Redundant) systems and towards dual redundant and networked control systems. Woodward’s core fuel and combustion control is currently being used in a networked system for GE’s LM2500 aeroderivative gas turbine packages. This networked control system utilizes redundant high-speed communications from the sequencer to fuel control. Packaging I/O is also distributed over redundant communications to localize wiring. The fuel control communicates to the gas metering valves and gas turbine variable geometry servo-valves to reduce wiring and installation time. This control system utilizes simplex CPU’s to save cost and duplex hardware and communications for availability. Expansion of this to full redundant CPU processing capabilities can also be achieved to add availability with some cost tradeoff. Woodward has also applied this full redundancy concept in the commercial marine GE LM2500 package applications. In addition to using network communications the core fuel control system is in itself networked, being “package” mounted. Mounting the fuel control on the package reduces the number of field installation wire terminations and the total length of wire used between the gas turbine and the fuel control. Having the main fuel control system mounted on the package allows the control to be wired and tested at the factory rather than at site. The use of network communications in gas turbine control applications has many advantages. Reduction in overall system cost, installation and commissioning time are the main advantages to using networked controls for gas turbines. System expandability and distributed processing are other advantages. Expanding this with hardware redundancy improves availability.

In the design of Fault Tolerant Systems, some type of hardware redundancy is often used, Triple Modular Redundancy being one of the well known techniques of this type. Anyway, it must be taken into account that, after one of the copies of the implemented hardware fails, then it loses fault mitigation ability and continues in operation degraded to self-checking pair. In today's dependable systems fault mitigation techniques are combined with techniques for the system repair and recovery. In FPGA-based systems the recovery process can be implemented by Partial Dynamic Reconfiguration process. In this paper, previously developed Fault Tolerant CAN Bus Control system and the FPGA partial reconfiguration process are combined to achieve the control system self-repairing ability. The synchronization process of the recovered circuit copy with the rest of the system which was operating while the faulty component reconfiguration was performed, is described in the paper.

The hunt for increased reliability in systems for critical applications is a never-ending process and is a point of concern for designers in several different fields, such as nuclear reactors. This concern becomes more prominent when a new device technology is integrated into the options for the development of those systems, such as programmable logic devices like the FPGA. With the constant breakthroughs in this technology, there has been an increase in the capacity and the performance of FPGAs. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. This work proposes a resilient and adaptable hardware architecture that increases the reliability of circuits implemented in FPGAs, based on a classic active redundancy model, Triple Modular Redundancy with spares. Also, it brings forth a novel hardware architecture that can easily be ported to different FPGA models without compromising performance, reliability, and availability. We discuss and analyze these requirements for the proposed architecture and show that it is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area.

This paper presents a method for liquid level stabilization using a fuzzy logic algorithm implemented on the PLC S7-1200. Maintaining liquid levels accurately is a critical requirement in various industrial processes to ensure safety, efficiency, and consistent product quality. The proposed approach employs fuzzy logic to manage the inherent nonlinearities and uncertainties in the system, providing robust control performance under varying operating conditions. The fuzzy controller is designed with rules and membership functions tailored to the dynamic characteristics of the liquid level system. The control logic is programmed and deployed on the Siemens PLC S7-1200, a widely used industrial automation device. Experimental results demonstrate that the fuzzy logic controller effectively stabilizes the liquid level, achieving better performance compared to traditional PID controllers in terms of response time, overshoot, and steady-state error. This study highlights the potential of integrating fuzzy logic with PLCs for advanced industrial automation applications.

We propose a set of procedures addressing the implementation of statechart models. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. The framework is the design of embedded systems (in the sense of reactive realtime systems) and automation applications, either industrial automation or building automation, either the emphasis is on system, hardware or software levels, using or not codesign techniques. An application focused on hardware implementation using VHDL as implementation language is used as an example.

Automatic Generation of Diverse Software Channels by Means of Arithmetic Codes